JPS6112293B2 - - Google Patents
Info
- Publication number
- JPS6112293B2 JPS6112293B2 JP55028502A JP2850280A JPS6112293B2 JP S6112293 B2 JPS6112293 B2 JP S6112293B2 JP 55028502 A JP55028502 A JP 55028502A JP 2850280 A JP2850280 A JP 2850280A JP S6112293 B2 JPS6112293 B2 JP S6112293B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- logic
- memory
- memory cells
- shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 26
- 238000010586 diagram Methods 0.000 description 4
- 239000000872 buffer Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000003745 diagnosis Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 235000014755 Eruca sativa Nutrition 0.000 description 1
- 244000024675 Eruca sativa Species 0.000 description 1
- 230000003915 cell function Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2850280A JPS56124957A (en) | 1980-03-06 | 1980-03-06 | Logical test circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2850280A JPS56124957A (en) | 1980-03-06 | 1980-03-06 | Logical test circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56124957A JPS56124957A (en) | 1981-09-30 |
| JPS6112293B2 true JPS6112293B2 (enrdf_load_stackoverflow) | 1986-04-07 |
Family
ID=12250444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2850280A Granted JPS56124957A (en) | 1980-03-06 | 1980-03-06 | Logical test circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56124957A (enrdf_load_stackoverflow) |
-
1980
- 1980-03-06 JP JP2850280A patent/JPS56124957A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56124957A (en) | 1981-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0463480B2 (enrdf_load_stackoverflow) | ||
| JP3645294B2 (ja) | 半導体メモリ装置の多重ビットテスト回路 | |
| JP4024582B2 (ja) | 多機能直列入力/出力回路 | |
| JP3022990B2 (ja) | 種々の検査パターンを有する並列検査による半導体メモリの検査回路装置 | |
| JPH071493B2 (ja) | テスト補助回路 | |
| JPH0750100A (ja) | アドレスバッファ | |
| US5378934A (en) | Circuit having a master-and-slave and a by-pass | |
| JPH07262797A (ja) | 半導体集積回路装置 | |
| JP2500932B2 (ja) | レベル感知ラツチ段 | |
| US5574857A (en) | Error detection circuit for power up initialization of a memory array | |
| US4682331A (en) | Logic circuit with self-test | |
| US5339320A (en) | Architecture of circuitry for generating test mode signals | |
| JPS6112293B2 (enrdf_load_stackoverflow) | ||
| CN101246739A (zh) | 存储装置 | |
| JPS6211382B2 (enrdf_load_stackoverflow) | ||
| JP2870291B2 (ja) | 半導体記憶回路 | |
| JPH0394350A (ja) | 半導体記憶装置 | |
| JPH047038B2 (enrdf_load_stackoverflow) | ||
| KR100345673B1 (ko) | 자기 진단 가능한 집적 회로 | |
| JPS6144342B2 (enrdf_load_stackoverflow) | ||
| JP2654604B2 (ja) | 論理回路 | |
| JP2877505B2 (ja) | Lsi実装ボード及びデータ処理装置 | |
| JPH06223597A (ja) | 半導体装置 | |
| JP3217548B2 (ja) | 半導体記憶装置 | |
| JPS58175192A (ja) | 読出/書込メモリ回路 |