JPS61117862A - High frequency circuit board - Google Patents

High frequency circuit board

Info

Publication number
JPS61117862A
JPS61117862A JP23968484A JP23968484A JPS61117862A JP S61117862 A JPS61117862 A JP S61117862A JP 23968484 A JP23968484 A JP 23968484A JP 23968484 A JP23968484 A JP 23968484A JP S61117862 A JPS61117862 A JP S61117862A
Authority
JP
Japan
Prior art keywords
line
high frequency
circuit board
frequency signal
feed line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23968484A
Other languages
Japanese (ja)
Inventor
Yukio Akazawa
幸雄 赤澤
Tsutomu Wakimoto
脇本 力
Masami Terasawa
正己 寺澤
Takanori Kubo
貴則 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Kyocera Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp, Nippon Telegraph and Telephone Corp filed Critical Kyocera Corp
Priority to JP23968484A priority Critical patent/JPS61117862A/en
Publication of JPS61117862A publication Critical patent/JPS61117862A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane

Abstract

PURPOSE:To improve the band characteristic, isolation characteristic, and gain flat characteristic by a method wherein an organic polymer is used as the dielectric, and resistance is alternatingly added by surrounding high frequency signal lines with a ground conductor, and by making the power source feed line as the distributed constant line of low characteristic impedance. CONSTITUTION:The organic polymer capable of lamination is used as the dielectric, and the high frequency signal line 16 is surrounded with ground conductors 14 and 17; thereby, the line width of said line 16 is made very small, and the coupling among high frequency signal lines can be inhibited. Besides, the characteristic impedance of a power source feed line 13 coming to distributed constant is reduced, thus constructing this line by termination with a resistor 18, and a high frequency signal line 16 is completely isolated from the power source feed lines 13 with the ground conductors 14 and 17. Thereby, the impedance of the power source feed line 13 in view from the power source terminal of a TC chap 19 is changed to pure resistance, resulting in the suppression of the effect of electrical feedback around the power source.

Description

【発明の詳細な説明】 (発明の技術分野) 本発明は、高周波トランジスタチップあるいは工Cチッ
プを用いて高周波電気回路装置を構成する際に使用する
電気回路基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an electric circuit board used when constructing a high frequency electric circuit device using a high frequency transistor chip or an engineered C chip.

(従来の技術) 第4図は従来の高周波回路基板例である。(alは上か
らみた平面図、(至)は断面図であって、lは誘電体、
2は金属基板、3は高I!1波信号線、4は電源フィー
ド線、5は接地導体、6は工Cチップ、7はチップコン
デンサ、8はポンディングワイヤである。本基板例は高
周波回路基板では特に接地電位を良好にとる必要がある
ことと、ICチップ6の発熱を押えることのために金属
基板2の中央に突起を設け、この突部と一致するように
穴を開けたセラミック等の誘電体1を貼り合せた構造と
し、突起した金属基板部分に直接工Cチップ、トランジ
スタチップを搭載するようにしたものである。従来この
ような回路基板上に工Cチップ等の能動部品を搭載して
、広帯域な増幅回路等を実現することがよく行なわれて
いる。この場合高周波信号線3については、装置の特性
インピーダンスと整合をとるため例えば50Ω、75Ω
の特性インピーダンスが実現できるように考慮して誘電
体1を適訳し設計を行なっている。
(Prior Art) FIG. 4 shows an example of a conventional high frequency circuit board. (Al is a plan view seen from above, (to) is a cross-sectional view, l is a dielectric,
2 is a metal substrate, 3 is a high I! 1-wave signal line, 4 is a power feed line, 5 is a ground conductor, 6 is an engineered C chip, 7 is a chip capacitor, and 8 is a bonding wire. In this board example, a protrusion is provided in the center of the metal substrate 2 in order to keep the ground potential particularly good in a high frequency circuit board and to suppress heat generation of the IC chip 6. It has a structure in which a dielectric material 1 made of ceramic or the like with holes is bonded together, and a C chip and a transistor chip are directly mounted on the protruding metal substrate portion. Conventionally, it has been common practice to mount active components such as a C chip on such a circuit board to realize a wideband amplifier circuit or the like. In this case, the high frequency signal line 3 should be, for example, 50Ω or 75Ω in order to match the characteristic impedance of the device.
The dielectric 1 is appropriately translated and designed in such a way that a characteristic impedance of .

この極のm電体としては従来基板厚0.64 fl程度
のアルミナ基板がよく用いられており、50Ωあるいは
75Ωの特性インピーダンスを持つ高周波信号線3は通
常マイクロストリップラインにより構成され、本アルミ
ナ基板を用いた場合、50Qの高周波信号llA3の線
幅は0.6Jfl程度となる。また数置角の工Cチップ
を実装する場合、 in波信号纏3はICチップ6をは
さんで数舖の間隔で向い合うことになる。そのため高周
波信号Is3間に該信号fl3間の間隔が数置と小さい
こと及び線幅がOB−程度と比較的大きいこと等から容
量性の結合が生じてしまい入出力間のアイソレージ震ン
が劣化するという問題がある。fJ5図は第4図に示す
高FI4波回路基板において基板厚0.64alのアル
ミナ基板に間隔3.5 a%N 0.64 gの高周波
信号線を形成した際の入出力間のアイソレージ1ン特性
の実測結果である。第5図から明らかなと諮り、アイソ
レージ1ン特性は2 Ga15で−50(IB程度であ
り安定性の点から2G−で50aBJl上の利得をもつ
工Cチップの実装は不可能となる。
Conventionally, an alumina substrate with a substrate thickness of about 0.64 fl is often used as the m-electric body of this pole, and the high frequency signal line 3 having a characteristic impedance of 50Ω or 75Ω is usually constituted by a microstrip line, and this alumina substrate When using, the line width of the 50Q high frequency signal llA3 is about 0.6 Jfl. Furthermore, when mounting a C-chip of several angles, the in-wave signal wires 3 will face each other with the IC chip 6 in between at intervals of several angles. Therefore, capacitive coupling occurs between the high frequency signals Is3 and the signal fl3 because the interval between them is as small as several orders of magnitude, and the line width is relatively large, about OB-, resulting in deterioration of isolation between input and output. There is a problem. Figure fJ5 shows the isolation between input and output when high-frequency signal lines with a spacing of 3.5 a%N and 0.64 g are formed on an alumina substrate with a substrate thickness of 0.64 al in the high FI 4-wave circuit board shown in Figure 4. These are the results of actual measurement of characteristics. As is clear from FIG. 5, the isolation characteristic is approximately -50 (IB) at 2Ga15, and from the viewpoint of stability, it is impossible to mount an engineered C chip with a gain of over 50aBJl at 2G-.

このアイソレージ1ン特性を改善するには高周波信号線
を細くすればよく、細くするためには誘電体の基板厚を
非常に薄くするか、あるいは誘電率を大きくすればよい
。しかし乍ら誘電率を大きくした場合、隣接する配線パ
ターンとの結合が大となるため誘電体厚を薄くするのが
最も有効であるが従来のアルミナ基板等では取扱いの点
から厚さ0.2&l程度が限界でありアイソレージ黛ン
の改善ができないという欠点を有していた。
In order to improve this isolation characteristic, the high frequency signal line can be made thinner, and in order to make it thinner, the thickness of the dielectric substrate can be made very thin, or the dielectric constant can be increased. However, if the dielectric constant is increased, the coupling with adjacent wiring patterns becomes large, so it is most effective to reduce the dielectric thickness. It has the disadvantage that the degree of isolation is limited and it is not possible to improve the isolation level.

また一方、電源フィード8I4については、インピーダ
ンスをもってしまうと交流的な接地が完全でなくなり、
正帰還や負帰還が生じ、入出力のアイソレージ層ンの劣
化、帯域特性の劣化、利得特性の平坦さの劣化などが生
じるため、極力低インピーダンス化が図られるように考
慮してパターン設計を行なっている。しかしながら、集
積回路技術の進歩により、搭載する工Cチップが高性能
多機能化が進み、信号線数と電源線数が増加し、実装回
路基板パターンが増々複雑化し、パターンが密となり、
線幅を細くせざるを得ず、$1!源線のインピーダンス
が大きくなり、また、周波数特性も増々広帯域化し、電
源線のインピーダンスが無視できないものとなっている
On the other hand, if the power supply feed 8I4 has impedance, the AC grounding will not be complete.
Positive feedback and negative feedback occur, resulting in deterioration of the input/output isolation layer, deterioration of band characteristics, deterioration of flatness of gain characteristics, etc., so the pattern should be designed with consideration to lower impedance as much as possible. ing. However, with the advancement of integrated circuit technology, the mounted C chips have become more high-performance and multifunctional, the number of signal lines and power supply lines has increased, and the patterns of mounted circuit boards have become increasingly complex and dense.
I had to make the line width thinner, which cost me $1! The impedance of the power supply line has become larger and the frequency characteristics have become increasingly broadband, making the impedance of the power supply line no longer negligible.

fJ6図(al (blは、電源パターンのインダクタ
ンスの影響を示すためのシミエレーシ膚ン特性である想
定したICチップはgJ6図(C)に示す並列帰還増幅
回路である。四が881(利得)特性、(1))がSt
g(アイソレージ履ン)特性である。数mlのインダク
タンスL、L8をD)(e)に示すように持った場合で
も利得及びアイソレージ1ン特性が大きく劣化すること
がわかる。
fJ6 diagram (al) (bl is the shimierance characteristic to show the influence of the inductance of the power supply pattern. The assumed IC chip is the parallel feedback amplifier circuit shown in gJ6 diagram (C). 4 is the 881 (gain) characteristic , (1)) is St
g (isolation wear) characteristic. It can be seen that even when several ml of inductances L and L8 are used as shown in D) (e), the gain and isolation characteristics are significantly degraded.

第7図は、上述の劣化を押えるために、一般に良く行な
われている手法として、ICチップ6の近傍でチップコ
ンデンサ7を電源のインピーダンスを小さくするように
接続した回路基板11のSat特性及びS1g特性の例
である。接続法は(Q) )C示す通りであり、ゆ)は
その等価回路である。なお/翫ツチングで示すラインは
分布定数Mg([1,5&l。
FIG. 7 shows the Sat characteristics and S1g of a circuit board 11 in which a chip capacitor 7 is connected in the vicinity of an IC chip 6 so as to reduce the impedance of the power supply, as a commonly used method to suppress the above-mentioned deterioration. This is an example of a characteristic. The connection method is as shown in (Q))C, and y) is its equivalent circuit. Note that the line indicated by / is the distribution constant Mg ([1,5&l.

厚さ0.64 fl )である。この場合は、ボンディ
ングワイヤおよび電源フィード線のインダクタンスとチ
ップコンデンサの容量とにより共振を生じ、S12特性
及びSit特性に共振特性が生じ、局所的Iζ利得特性
およびアイソレージ鱈ン特性が劣化するといった問題が
あり、広帯域の増幅回路の実現という観点から大きな問
題があった。
The thickness is 0.64 fl). In this case, resonance occurs due to the inductance of the bonding wire and power feed line and the capacitance of the chip capacitor, causing resonance characteristics in the S12 characteristics and Sit characteristics, and causing problems such as deterioration of the local Iζ gain characteristics and isolation characteristics. However, there were major problems from the viewpoint of realizing a wideband amplifier circuit.

(発明の目的) 本発明は膜厚を非常に薄くすることが可能な有機高分子
材料を誘電体として用い、高、R波信号線幅を小さく、
かつ高周波信号線を接地導体で取囲む構造とし、高周波
信号線間の結合を抑止するとともに電源フィード線を特
性インピーダンスの小さい線絡とし交流的にその特性イ
ンピーダンスで終端すること、電源フィード線の面積を
できる限り大きくとり、かつ誘電体厚を薄くすることで
容量をもたせ低インピーダンス化することにより利得特
性の平坦化、広帯域化、及びアイソレージ翳ン特性の改
善を可能とした高周波回路基板を墨供することを目的と
するものである。
(Objective of the Invention) The present invention uses an organic polymer material that can be made very thin in film thickness as a dielectric material to reduce high and R wave signal line widths.
In addition, the high-frequency signal line is surrounded by a ground conductor to prevent coupling between the high-frequency signal lines, and the power feed line is connected to a wire with a small characteristic impedance and terminated at that characteristic impedance for alternating current, and the area of the power feed line is To provide a high frequency circuit board that makes it as large as possible and thins the dielectric thickness to increase capacitance and lower impedance, thereby making it possible to flatten the gain characteristics, widen the band, and improve the isolation shadow characteristics. The purpose is to

(発明の構成及び作用) 以下1本発明の詳細な説明する。(Structure and operation of the invention) The present invention will be explained in detail below.

第1図は本発明の高周波回路基板の一実施例を示し、1
1は金属基板、12及び15は誘電体、13は分布定数
化された電源フィード線、14及び17は接地導体、1
6は高周波信号線、18はI11膜抵抗、19は工Cチ
ップである。本発明は従来の第4図の例3ζ対し、高周
波信号線を歓細化するとともに完全に接地導体で取囲み
隣接する信号#1間の結合を抑止する構造としたもので
ある。更には電源フィード線及び高周波信号線を同一の
基板上に容易に形成し得るようにしたものである。1t
aL2は電源フィード纏13の特性インピーダンスを1
Ω程度以下に下げるため非常に薄い厚みに形成されてい
る。この誘電体12はポリイミド等の有機高分子フェス
をスプレーコート法等により金属基板ll上に形成され
、その厚みはS#程度の極めて薄い厚みに形成される。
FIG. 1 shows an embodiment of the high frequency circuit board of the present invention.
1 is a metal substrate, 12 and 15 are dielectrics, 13 is a distributed power supply feed line, 14 and 17 are ground conductors, 1
6 is a high frequency signal line, 18 is an I11 film resistor, and 19 is an engineered C chip. In contrast to the conventional example 3ζ shown in FIG. 4, the present invention has a structure in which the high frequency signal line is thinned and completely surrounded by a ground conductor to prevent coupling between adjacent signals #1. Furthermore, the power feed line and the high frequency signal line can be easily formed on the same substrate. 1t
aL2 is the characteristic impedance of the power supply feed line 13, which is 1
It is formed with a very thin thickness in order to reduce the thickness to about Ω or less. This dielectric 12 is formed by spray coating an organic polymer layer such as polyimide on a metal substrate 11, and has a very thin thickness of approximately S#.

またEi1′?IL体15は高周波信号線16における
信号の伝搬遅逼時間を短かくするため比誘電率が5以下
の有機高分子を用い、高周波信号線16の特性インピー
ダンスを50Ωあるいは75Qに設計するために適当な
厚みを要している。実際Cζは高周波信号線16の幅を
50μ肩とすると誘電体15の厚みを約100μmにす
ることにより特性インピーダンスを50Ωと為すことが
可能となる。
Ei1′ again? The IL body 15 is made of an organic polymer having a dielectric constant of 5 or less in order to shorten the propagation delay time of the signal in the high frequency signal line 16, and is suitable for designing the characteristic impedance of the high frequency signal line 16 to 50Ω or 75Q. It requires a certain thickness. In fact, when the width of the high-frequency signal line 16 is set to 50 μm, the characteristic impedance of Cζ can be set to 50 Ω by making the thickness of the dielectric 15 approximately 100 μm.

を交流的にその特性インピーダンスで終端するものであ
り、従来周知の薄膜技術で形成される。
AC is terminated with its characteristic impedance, and is formed using conventionally well-known thin film technology.

次に、本発明の高周波回路基板の製造方法を詳述する。Next, a method for manufacturing a high frequency circuit board according to the present invention will be described in detail.

まず第1図に示すように金属基板11上に低誘電率有機
高分子ワニスをスピンコード法又はスプレーコート法に
より塗布しホトリソグラフィ技術によりパターン加工し
たのち、高温キュアし、低誘電率絶縁パターンを形成す
る。次にイオンブレーティング法及びスパッタ法により
導体薄膜を形成し、ホトリソグラフィ技術により、分布
定数#l&!−となるよう同−線幅の電源フィード!1
113を形成する。ここで電源フィード線13を誘電体
で取囲む帽1ζするため、再度、その上に低誘電率絶縁
パターンを前記と同様の方法により形成しこれによりi
!lta体12内体重2内ィード線13を埋入する。
First, as shown in FIG. 1, a low dielectric constant organic polymer varnish is applied onto a metal substrate 11 using a spin code method or a spray coating method, patterned using photolithography technology, and then cured at a high temperature to form a low dielectric constant insulating pattern. Form. Next, a conductor thin film is formed by ion blating method and sputtering method, and distributed constant #l & ! is formed by photolithography technology. -Power supply feed with the same line width so that it is -! 1
113 is formed. Here, in order to surround the power feed line 13 with a dielectric material, a low dielectric constant insulating pattern is again formed on it in the same manner as described above.
! Insert the lead wire 13 inside the weight 2 inside the lta body 12.

以下、下記に示す方法により順次、積層していく。Thereafter, the layers are sequentially laminated by the method shown below.

接地導体14は蒸着イオンブレーティング法又はスパッ
タ法により膜を形成するが、WX形成と同時fζパター
ン化するマスク蒸着により、パターン形成する。誘電体
重5は誘電体12と同様の方法により形成する。高周波
信号M16は、マスク蒸着したのちホトリソグラフィ技
術により、形成する。最後に、最上層である接地導体1
7は、接堺導体14と同様の方法により形成し、表面処
理を施し、完成となる。
The ground conductor 14 is formed into a film by a vapor deposition ion-blating method or a sputtering method, and the pattern is formed by mask vapor deposition to form an fζ pattern at the same time as WX formation. The dielectric weight 5 is formed by the same method as the dielectric 12. The high frequency signal M16 is formed by photolithography after mask deposition. Finally, the top layer, the ground conductor 1
7 is formed by the same method as the grounding conductor 14, subjected to surface treatment, and completed.

ここで、この製造方法の特筆すべきことは、低誘電率有
機高分子ワニスがスピンコード法又ハ。
What is noteworthy about this manufacturing method is that the low dielectric constant organic polymer varnish can be produced using the spin code method or c.

スプレーコート法により、フェスの粘度及びスピンコー
ドであればスピン回転数を変えることで容易に数ミクロ
ンのll1IIIから数十ミクロンの厚膜まで厚みを形
成できる特徴をもち、またそれら厚みの異なる誘電体を
同一基板上に形成することが可能であることである。
The spray coating method has the characteristic that it can easily form thick films from several microns to several tens of microns by changing the viscosity of Fes and the spin speed in the case of spin code, and it is also possible to form thick films from several microns to several tens of microns. It is possible to form both on the same substrate.

以上のように、本発明は膜厚を薄くすることが可能な有
機高分子を誘電体として用いるとともに高周波信号m1
6を接地導体14及び17で取囲む構造としたことによ
り高周波信号線16の線幅を極めて細いものと為すこと
ができ、かつ高周波信号線間の結合を抑止することがで
きる。また分布定数化した電源フィード!113の特性
インピーダンスを下げ抵抗18により終端する構成とす
るとともに高周波信号線16と電源フィード線13を接
地導体14及び17で完全に分離する構造としたことに
より工Cチップ19の電源端子からみた電源フィード1
i13のインピーダンスを純抵抗化し、 しかもその抵
抗値を小さく為すことができ電源まわりの電気的な帰還
効果を抑圧するとともに電源フィード線13から高R1
1信号I!16に与える信号ライン特性の悪影響も防止
できる。これにより高周波回路基板としての帯域特性の
劣化、利得特性の平坦特性の劣化、およびアイソレージ
冒ン特性の劣化が有効に阻止される。電源フィード線の
効果のシェミレーシ望ン結果を第2図に示す。尚シェミ
レーシ冒ン回路は第6図に示す回路を使用した。第2図
中破線■が電源ラインに長さ10tlIWIの特性イン
ピーダンスZθ冨50Ωのラインを用いて終端しない場
合、一点鎖線■が50Qで終端した場合、実線■が上述
したように低くした特性インピーダンス0.58Ωのf
Ii源フィード線を用いた場合である。
As described above, the present invention uses an organic polymer that can be made thinner as a dielectric material, and also transmits a high frequency signal m1.
6 is surrounded by ground conductors 14 and 17, the line width of the high frequency signal line 16 can be made extremely narrow, and coupling between the high frequency signal lines can be suppressed. Also, a distributed constant power supply feed! By lowering the characteristic impedance of 113 and terminating it with a resistor 18, the high-frequency signal line 16 and power feed line 13 are completely separated by ground conductors 14 and 17. feed 1
The impedance of i13 can be made into a pure resistance, and the resistance value can be made small, suppressing the electrical feedback effect around the power supply and allowing high R1 from the power supply feed line 13.
1 signal I! It is also possible to prevent the adverse effects of the signal line characteristics on the 16. This effectively prevents deterioration of band characteristics as a high frequency circuit board, deterioration of flatness characteristics of gain characteristics, and deterioration of isolation characteristics. The desired shemirelation result of the effect of the power feed line is shown in FIG. The circuit shown in FIG. 6 was used as the simulation circuit. In Fig. 2, the broken line ■ indicates that the power supply line is not terminated using a line with a length of 10tlIWI and a characteristic impedance Zθ of 50Ω, the dashed line ■ terminates at 50Q, and the solid line ■ indicates the lowered characteristic impedance 0 as described above. .58Ω f
This is the case when the Ii source feed line is used.

一点#4M■の場合はICチップエ9の電源端子からみ
たインピーダンスが純抵抗となっていることがわかる。
It can be seen that in the case of one point #4M■, the impedance seen from the power supply terminal of the IC chip E 9 is pure resistance.

また、実線@の場合には、工Cチフプ19と実装基板の
接続のためのボンディングワイヤのインダクタンスの効
果だけが現れるようになり、実装回路基板の影響が殆ん
どなくなりでいることがわかる。従来の第7図の特性に
比べ大きくアインレーシ曽ン特性、帯域特性利得の平坦
さを改善することができる。
Furthermore, in the case of the solid line @, only the effect of the inductance of the bonding wire for connecting the circuit chip 19 and the mounted circuit board appears, and it can be seen that the influence of the mounted circuit board is almost eliminated. Compared to the conventional characteristics shown in FIG. 7, it is possible to greatly improve the flatness of the inlay frequency characteristics and band characteristic gain.

ここで、電源フィード線13の終端抵抗18を用いない
場合に甘いても電[フィード4113の特性インピーダ
ンスがIQ程度と小さく、現実の場合は、フィード纏に
損失があるので終端しな(でも初期の効果を太き(損な
うことがな(作用効果は同様である。
Here, if the terminating resistor 18 of the power feed line 13 is not used, the characteristic impedance of the electric power feed 4113 is as small as IQ, and in reality, there is loss in the feed line, so it is not necessary to terminate it (but the initial It thickens (does not impair) the effect of (the effect is the same).

第3図は本発明の高尚波回路基板の他の実施例を示し、
21は金属基板、22及び25は誘電体、23は電源フ
ィード纏、24及び27は接地導体、26は高周波信号
線、29は工Cチップである。この実施例は電源フィー
ド纏23の線幅を可能な限り広くとっている点で実施例
1と異なっている。このように電源フィード5123の
!llKを可能な限り広くとると電源フィード線23は
100FF以上の大きな静電容量を有することとなり電
源フィードts23は極メチ低インピーダンスのライン
となって実施例1と同様の作用効果を奏することが可能
となる。
FIG. 3 shows another embodiment of the high frequency circuit board of the present invention,
21 is a metal substrate, 22 and 25 are dielectrics, 23 is a power supply feed, 24 and 27 are ground conductors, 26 is a high frequency signal line, and 29 is an engineered C chip. This embodiment differs from the first embodiment in that the line width of the power feed bundle 23 is made as wide as possible. In this way the power feed 5123! If llK is set as wide as possible, the power feed line 23 will have a large capacitance of 100FF or more, and the power feed ts23 will become a line with extremely low impedance, making it possible to achieve the same effects as in the first embodiment. becomes.

尚、この高周波回路基板は実施例1と同じ方法により製
造される。
Note that this high frequency circuit board is manufactured by the same method as in Example 1.

(発明の効果) 以上、説明したように本発明は有機高分子を誘電体とし
て用い、かつ高周波信号線を接地導体で取囲むととも+
c 1!! 11フイード線を低特性インピーダンスの
分布定数線路とし交流的に抵抗を付加するなどして終端
する構成とし、工Cチップあるいはトランジスタチップ
の電源端子からみたインピーダンスを低抵抗値の純抵抗
化することにより信号線間の結合、およびIl源まわり
の回路基板による帰還効果を抑圧することができ、帯域
特性、アインレーシ1ン特性、利得の平坦特性を改善し
得る利点がある。
(Effects of the Invention) As explained above, the present invention uses an organic polymer as a dielectric, and surrounds a high frequency signal line with a ground conductor.
c1! ! By making the 11 feed line a distributed constant line with low characteristic impedance and terminating it by adding a resistance in an AC manner, the impedance seen from the power supply terminal of the C chip or transistor chip is made into a pure resistor with a low resistance value. This has the advantage that coupling between signal lines and feedback effects due to the circuit board around the Il source can be suppressed, and band characteristics, in-resistance characteristics, and gain flatness characteristics can be improved.

また電源フィード線と接地導体との間の誘電体厚を10
μ屑程度とし、その静電容量を太き(して低インピーダ
ンス化することにより上述と同様の利点が得られる。
Also, the dielectric thickness between the power feed line and the ground conductor is 10
The same advantages as described above can be obtained by making the capacitance as large as a μ-sized piece and increasing the capacitance (thus lowering the impedance).

更に、誘電体として、有機高分子を用いることによって
aII厚が異なる二種以上の誘電体を同−基板上憂ζ任
意に作製することが可能であり、その結果低インピーダ
ンスの電源フィルド線と50Ωもしくは75Ωの特性イ
ンピーダンスをもつ高周波信号線を同一基板上に形成し
得る利点を有している。
Furthermore, by using organic polymers as dielectrics, it is possible to arbitrarily produce two or more types of dielectrics with different thicknesses on the same substrate, and as a result, a low impedance power supply line and a 50Ω Alternatively, it has the advantage that a high frequency signal line having a characteristic impedance of 75Ω can be formed on the same substrate.

また誘電体は比誘電率を5以下にすることができKR波
信号線を伝搬する信号を高速と為すこともできる。
Further, the dielectric material can have a dielectric constant of 5 or less, and the signal propagating through the KR wave signal line can be transmitted at high speed.

更に数1厚の金属板を基板として用い、その上に工Cチ
ップを直接搭載するため熱放散が改善され、工Cチップ
の発熱を防止するという効果がある。また、同様の理由
から接地電位が高周波動作時にも安定化され、接地電位
の変動に伴なう不安定動作特性劣化を防止するという効
果がある。更に、同様の理由から、チップ上面をお右う
ふたとして数n厚の金属板を用いれば、ICチップが上
下厚い金属板によりはさまれた構造となり宇宙環境にあ
ける放射譲から工Cチップを保護するという効果がある
Furthermore, since a metal plate several tens of meters thick is used as the substrate and the C-chip is directly mounted on it, heat dissipation is improved and heat generation of the C-chip is prevented. Further, for the same reason, the ground potential is stabilized even during high frequency operation, and there is an effect of preventing deterioration of unstable operation characteristics due to fluctuations in the ground potential. Furthermore, for the same reason, if a metal plate several nanometers thick is used with the top surface of the chip as the right cover, the IC chip will have a structure sandwiched between the upper and lower thick metal plates, making it difficult for the IC chip to be exposed to radiation in the space environment. It has the effect of protecting.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(alは本発明の高周波回路基板の一部破断斜視
図、第1図(b)ハ第1図(ag)a −a’腺断面図
、第2図(al及び(′b)は第1図の高周波回路基板
のば理的な効果を説明するための回路特性柄図、第3図
四は本発明の他の実施例を示す一部破断斜視図、第3図
中)は第3図れ)のa−a’線断面図、第4図(atは
従来の高周波回路基板の平面図、14図(′b)は第4
図(a)の断Wi図、第5図は第45inの高周波回路
基板の回路特性柄図、第6図(all鴫、 (Ql 、
 (d) 、 Telは従来の高周波回路基板H−怠け
る電源プイード線のインピーダンスの回路特性に及ぼす
効果を示す特性図及びその使用回路図と等価回路図、第
7図(al、 (’b)、 (C1,((1)は従来の
高周波回路基板1こよる回路2.11.21−金属基板 4.13.23−電源フィード線 3.16.26 −信   号   線6.19.29
−ICチップ 18−−−、−抵抗 特許出願人 (442)日本電信電話公社(663)京
セラ株式会社 ミ さ)〉Δ−へ■ス た 第3図 第4図 (b) cet     =    ンφ 1    曹6    zw 胃 )ト)〉ニー)mへ セ 喝へ \  Q 用 シ虻 数 (6H乙ン 潟町
Fig. 1 (al is a partially cutaway perspective view of the high frequency circuit board of the present invention, Fig. 1 (b) c) Fig. 1 (ag) a-a' sectional view, Fig. 2 (al and ('b) 1 is a circuit characteristic diagram for explaining the theoretical effect of the high frequency circuit board, FIG. 3 is a partially cutaway perspective view showing another embodiment of the present invention, Figure 3) is a cross-sectional view taken along line a-a', Figure 4 (at is a plan view of a conventional high-frequency circuit board, Figure 14 ('b) is a cross-sectional view of the fourth
Fig. 5 is a diagram of the circuit characteristics of the 45-inch high-frequency circuit board, Fig. 6 is a cross-sectional diagram of Fig. (a),
(d), Tel is a characteristic diagram showing the effect of the impedance of the idle power source wire on the circuit characteristics of the conventional high frequency circuit board H, and its usage circuit diagram and equivalent circuit diagram, Figure 7 (al, ('b), (C1, ((1) is a conventional high frequency circuit board 1 circuit 2.11.21 - metal board 4.13.23 - power feed line 3.16.26 - signal line 6.19.29
-IC chip 18---, -resistance patent applicant (442) Nippon Telegraph and Telephone Public Corporation (663) Kyocera Corporation Misa)> Cao 6 zw stomach) t)〉knee) m to sekai \ Q for shifu number (6H Otonagata Town

Claims (6)

【特許請求の範囲】[Claims] (1)電源フィード線の接地導体に対するインピーダン
スを低インピーダンスとしかつ高周波信号線を接地導体
で取囲み、当該電源フィード線と信号線を同一金属板上
に形成したことを特徴とする高周波回路基板。
(1) A high frequency circuit board characterized in that the impedance of the power feed line with respect to a ground conductor is low, the high frequency signal line is surrounded by a ground conductor, and the power feed line and the signal line are formed on the same metal plate.
(2)電源フィード線及び高周波信号線が比誘電率5以
下の有機高分子から成る誘電体中に埋入されていること
を特徴とする特許請求の範囲第1項に記載の高周波回路
基板。
(2) The high frequency circuit board according to claim 1, wherein the power feed line and the high frequency signal line are embedded in a dielectric material made of an organic polymer having a dielectric constant of 5 or less.
(3)電源フィード線が低特性インピーダンスの分布定
数線路であることを特徴とする特許請求の範囲第1項に
記載の高周波回路基板。
(3) The high frequency circuit board according to claim 1, wherein the power feed line is a distributed constant line with low characteristic impedance.
(4)電源フィード線の接地導体に対するインピーダン
スを低インピーダンスとしかつ高周波信号線を接地導体
で取囲み、当該電源フィード線と信号線を同一金属板上
に形成するとともに前記電源フィード線により給電され
る能動デバイスチップの電源端子からみたときのインピ
ーダンスが純抵抗にみえるように前記電源フィード線を
交流的に終端する抵抗を電源フィード線に配置したこと
を特徴とする高周波回路基板。
(4) The impedance of the power feed line with respect to the ground conductor is low, the high frequency signal line is surrounded by a ground conductor, the power feed line and the signal line are formed on the same metal plate, and power is supplied by the power feed line. 1. A high frequency circuit board, characterized in that a resistor is arranged on the power supply line to terminate the power supply line in an alternating current manner so that the impedance when viewed from the power supply terminal of an active device chip appears to be a pure resistance.
(5)電源フィード線及び高周波信号線が比誘電率5以
下の有機高分子から成る誘電体中に埋入されていること
を特徴とする特許請求の範囲第4項に記載の高周波回路
基板。
(5) The high frequency circuit board according to claim 4, wherein the power feed line and the high frequency signal line are embedded in a dielectric material made of an organic polymer having a dielectric constant of 5 or less.
(6)電源フィード線が低特性インピーダンスの分布定
数線路であることを特徴とする特許請求の範囲第4項に
記載の高周波回路基板。
(6) The high frequency circuit board according to claim 4, wherein the power feed line is a distributed constant line with low characteristic impedance.
JP23968484A 1984-11-13 1984-11-13 High frequency circuit board Pending JPS61117862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23968484A JPS61117862A (en) 1984-11-13 1984-11-13 High frequency circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23968484A JPS61117862A (en) 1984-11-13 1984-11-13 High frequency circuit board

Publications (1)

Publication Number Publication Date
JPS61117862A true JPS61117862A (en) 1986-06-05

Family

ID=17048370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23968484A Pending JPS61117862A (en) 1984-11-13 1984-11-13 High frequency circuit board

Country Status (1)

Country Link
JP (1) JPS61117862A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135102A (en) * 1987-10-02 1989-05-26 American Teleph & Telegr Co <Att> Ceramic package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50132466A (en) * 1974-04-08 1975-10-20
JPS517819U (en) * 1974-07-05 1976-01-21
JPS545761B2 (en) * 1974-06-10 1979-03-20
JPS5831428U (en) * 1981-08-26 1983-03-01 日本精工株式会社 track guide bearing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50132466A (en) * 1974-04-08 1975-10-20
JPS545761B2 (en) * 1974-06-10 1979-03-20
JPS517819U (en) * 1974-07-05 1976-01-21
JPS5831428U (en) * 1981-08-26 1983-03-01 日本精工株式会社 track guide bearing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135102A (en) * 1987-10-02 1989-05-26 American Teleph & Telegr Co <Att> Ceramic package

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