JPS61103747U - - Google Patents
Info
- Publication number
- JPS61103747U JPS61103747U JP18499584U JP18499584U JPS61103747U JP S61103747 U JPS61103747 U JP S61103747U JP 18499584 U JP18499584 U JP 18499584U JP 18499584 U JP18499584 U JP 18499584U JP S61103747 U JPS61103747 U JP S61103747U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- circuit
- data
- pull
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図はこの考案の実施例を示す構成図、第２
図はメモリアクセスエラー検出回路の従来例を示
す構成図である。
符号の説明、１１，１２……メモリ、２１，２
２……パリテイメモリ、３……ナンドゲート、４
……パリテイチエツク回路、５……インバータゲ
ート、６……ウオツチドツグタイマ回路、７……
データバス、８……アドレスバス、９，１０……
プルアツプ用抵抗。
Figure 1 is a configuration diagram showing an embodiment of this invention, Figure 2
The figure is a configuration diagram showing a conventional example of a memory access error detection circuit. Explanation of symbols, 11, 12...Memory, 21, 2
2...Parity Memory, 3...Nand Gate, 4
... Parity check circuit, 5 ... Inverter gate, 6 ... Watchdog timer circuit, 7 ...
Data bus, 8... Address bus, 9, 10...
Pull-up resistor.
Claims (1)
メモリと、個々のデータに対応するパリテイデー
タを該第１メモリのアドレスと対応付けて記憶す
る第２のメモリと、第１メモリから読み出される
データと対応するパリテイデータを生成しこれと
第２メモリから読み出されるパリテイデータとを
比較するパリテイチエツク回路と、前記第１およ
び第２メモリの各出力端子を抵抗を介してプルア
ツプするプルアツプ回路とを設け、メモリの未実
装領域または未実装メモリがアクセスされたとき
は該プルアツプ回路を介して前記パリテイチエツ
ク回路へ所定の信号を与えることにより、メモリ
アクセスエラーをパリテイチエツク回路にて検出
することを特徴とするメモリアクセスエラー検出
回路。 a first memory that stores predetermined data in correspondence with addresses; a second memory that stores parity data corresponding to individual data in association with addresses of the first memory; and data read from the first memory. and a pull-up circuit that pulls up each output terminal of the first and second memories via a resistor. A memory access error is detected by the parity check circuit by providing a predetermined signal to the parity check circuit via the pull-up circuit when an unimplemented area of the memory or an unimplemented memory is accessed. A memory access error detection circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18499584U JPS61103747U (en) | 1984-12-07 | 1984-12-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18499584U JPS61103747U (en) | 1984-12-07 | 1984-12-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61103747U true JPS61103747U (en) | 1986-07-02 |
Family
ID=30742477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18499584U Pending JPS61103747U (en) | 1984-12-07 | 1984-12-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61103747U (en) |
-
1984
- 1984-12-07 JP JP18499584U patent/JPS61103747U/ja active Pending
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