JPS6089188A - Correcting circuit of digital color signal - Google Patents

Abstract

PURPOSE:To control hue of a color signal with high accuracy by applying an input digital color difference signal as an address input of a memory. CONSTITUTION:A digital color difference signal extracted respectively from interpolation circuits 64, 65 is fed to a hue correction circuit 66. The circuit 66 adjusts the phase of color signal as the result of both color difference signals, i.e., hue by changing the value of the two color difference signals. The color difference signal from the circuit 66 and a luminance signal from a delay circuit 61 are fed to a digital matrix circuit 67 and a digital three-primary color signal being the output is fed to a color temperature correction circuit 38. A data for correction is fed to the circuits 66, 68 from a control section 69 comprising a microprocessor and a memory. The data for correction is designated by a control signal from a terminal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a color video signal correction circuit used in video cameras, color VTRs, etc., and particularly to a hue control circuit.

"Background Art and Problems Therein" Conventionally, when correcting the hue of an analog color video signal based on the NTSC system, it has been done by moving the phase of a subcarrier for color demodulation. However, the hue correction circuit using an analog circuit has poor temperature characteristics.
The disadvantages are that it changes over time and has poor stability, and it is also difficult to integrate the circuit and miniaturize it. Therefore, it is conceivable to digitize the analog color video signal and perform hue correction using a digital circuit. In this case, for example, if the phase is moved in steps of 1°, subcarriers with 360 different phases must be generated, which increases the memory capacity and complicates the configuration of the subcarrier generation circuit. .

``Object of the Invention'' The present invention is a color signal correction circuit that uses a digital circuit to provide high stability and is easy to integrate. The purpose is to provide circuits.

"Summary of the Invention" The present invention provides a digital color signal correction circuit for hue correction of a digital color signal, in which the phase of a color signal on color coordinates is changed by a predetermined amount in accordance with first and second color difference signals. A digital color signal correction circuit comprising means for generating a data conversion table, and a memory in which the data conversion table is written, and supplying first and second input digital color difference signals as address inputs of the memory. It is.

Embodiment FIG. 1 shows the overall configuration of a color video signal recording and reproducing apparatus to which the present invention can be applied. This color video signal recording/reproducing device uses a fixed magnetic head indicated by 1, and a magnetic sheet (not shown) is coated with one frame (one frame).
A color still image signal (which may be a field) is recorded as one or two circular tracks. One magnetic sheet is rotatably stored inside the hard shell,
It is possible to form dozens of circular tracks. This magnetic sheet cassette is small and can be used as a recording medium for a still image video camera.

FIG. 1 shows the configuration of signal processing when recording and reproducing color video signals. This signal processing will be summarized below.

First, this embodiment can record both, for example, an NTSC system composite color video signal and a component color video signal consisting of three primary color signals. The main playback output is a composite color video signal, and component color video signals are output for monitoring. The signal recorded on the magnetic sheet consists of an FM modulated luminance signal YFM and an FM modulated line sequential color signal. The center frequency fY of the signal YFM is a predetermined frequency within the range of 6 to 7.5 MHz, and the FM of the red color difference signal R-Y
The modulation center frequency fR is, for example, 1.2 MHz, and the FM modulation center frequency fB of the blue color difference signal B-Y is, for example, 1.2 MHz.
It is assumed to be 3MHz. These two color difference signals are line-sequentialized so that they appear alternately every IH (one horizontal period). By line sequentialization, the recording signal band can be narrowed. The reason why the center frequencies of the two color difference signals have an offset from each other is to identify a line-sequential color sequence.

In addition, most of the signal processing is performed digitally, thereby stabilizing the operation and facilitating the implementation of an integrated circuit configuration. Furthermore, the A/D converter provided on the input side of the signal processing section and the D/A converter provided on the output side thereof are as follows.
It is commonly used in both recording circuits and reproduction circuits.

A further D/A converter is provided to form a component color video signal for monitoring.

The configuration of signal processing for recording and reproduction will be described in further detail with reference to FIG. In Figure 1, 2 is an input terminal to which an NTSC color video signal is supplied, 3, 4 and 5 are input terminals from a color video camera, microcomputer, etc.
An input terminal 6 is supplied with the primary color signals R, G, and B, respectively, and an input terminal 6 is supplied with a composite synchronization signal 5YNC corresponding to a component video signal composed of the three primary color signals.

The three primary color signals are supplied to the matrix circuit 7 and converted into a luminance signal Y, a red color difference signal RY, and a blue color difference signal B-Y. Two color difference signals outputted from the matrix circuit 7 are supplied to the input terminal of the switching circuit 8, and the two color difference signals are supplied to the input terminal of the switching circuit 8.
The switching pulses from the IH are alternately taken out to the output terminal for each IH. This switching circuit 8 is
A line sequential color signal LSC is generated. In FIG. 1, the luminance signal is Y
, the red color difference signal and the blue color difference signal are represented as R-Y and B-Y, respectively, the composite color video signal is represented as NTSC, and the line sequential color signal is represented as L.
It is represented as SC, and each component of the three primary color signals is represented as R, G, and B.

11, 12. 13,14. 15. 16. 17
are recording/reproduction changeover switches, respectively. These recording/reproduction changeover switches 11 to 17 each have a recording side terminal (indicated by a black circle) and a reproduction side terminal (indicated by a white circle). FIG. 1 shows the connection state of these recording/reproduction changeover switches 11 to 17 during recording. 18 is a switch that can be switched depending on the difference between composite input and component input.

The composite color video signal from input terminal 2 is output to switch 18.
The brightness signal from the I/J control circuit 7 is supplied to the input terminal 20 of the switch 180, and one of the signals selected by the switch 18 is sent to the input terminal 19 of the switch 18 to A/D=+ is supplied to the inverter 31. Line sequential color signal LSC from switching circuit 8
is supplied to the A/D converter 32 via the recording/reproduction changeover switch 12.

The A/D converter 31 has 4 fsc (fsc i color sub gear 9f frequency) from the clock generation circuit 33.
sampling clock is supplied. A sampling clock from a clock generation circuit 33 is supplied to the A/D converter 32 via a divide-by-1 circuit . The output of each of these A/D converters 31 and 32 has 1
Digital data with a sample of 8 bits is obtained. The clock generation circuit 33 generates a sampling clock whose frequency and phase are synchronized with the input signal, and the sampling clock is supplied to the digital decoder 35 and the control data from the digital decoder 35 is transmitted to the clock generation circuit 33. supplied to

The output data of the A/D converter 31 is sent to the digital decoder 35 through the recording side terminal of the recording/reproduction changeover switch 13.
supplied to The digital decoder 35 separates the composite color video signal into a luminance signal and a carrier color signal;
A process of generating a control signal for the clock generation circuit 33 from a burst signal included in the carrier color signal, a process of digitally demodulating the carrier color signal, and converting two color difference signals that are demodulated outputs into a line sequential color signal LSC. and processing.

The luminance signal from the digital decoder 35 is supplied to a digital pre-emphasis circuit 41.

The line sequential color signal LSC from the digital decoder 35 has a sampling rate of 2fsc, and this line sequential color signal LSC is applied to one input terminal 37 of the switch 36.
supplied to A line sequential color signal LSC from the A/D converter 32 is supplied via the other switch 36.

The line sequential color signal passed through this switch circuit 36 is supplied to an adder circuit 39.

ID data is supplied to the adder circuit 39 from a terminal 40 . This ID data has different values between the line of the red color difference signal RY and the line of the blue color difference signal B-Y. Using this ID data, the frequency when FM modulation is not performed is made different between the two color difference signals. The output of the adder circuit 39 is sent to the digital pre-emphasis circuit 4.
2.

The respective outputs of pre-emphasis circuits 41 and 42 are supplied to digital FM modulators 43 and 44, and their modulated outputs are mixed by mixer 45.

The output of the mixer 45 is supplied to the D/A converter 46 through the recording side terminal of the recording/reproduction changeover switch 15. This D/A converter 46 supplies an analog recording signal with a frequency spectrum shown in FIG. be done. A recording signal is recorded on a magnetic sheet by this magnetic head 1.

A signal reproduced from the magnetic sheet by the magnetic head 1 is supplied to a bypass filter 52 and a low-pass filter 53 via a reproduction amplifier 51.

An FM-modulated luminance signal is taken out from the bypass filter 52, and an FM-modulated line-sequential color signal is taken out from the low-pass filter 53. The outputs of the bypass filter 52 and the low-pass filter 53 are supplied to analog FM demodulation circuits 54 and 55, and the respective demodulation outputs are supplied to de-emphasis circuits 56 and 57.

Luminance signal Y extracted from de-emphasis circuit 56
through the playback side terminal of the recording/playback switch 11
is supplied to the D converter 31, and this A/D converter 3
1 into a digital signal. The line sequential color signal LSC taken out from the de-emphasis circuit 57 is passed through the playback side terminal of the recording/playback changeover switch 12 to A/D.
is supplied to the converter 32, and this A/D converter 32
is converted into a digital signal by A digital luminance signal from the A/D converter 31 is supplied to the delay circuit 61 through the reproduction side terminal of the recording/reproduction changeover switch 13.

The digital line sequential color signal from the A/D converter 32 is supplied to the synchronization circuit 62 through the reproduction side terminal of the recording/reproduction changeover switch 14 .

The synchronization circuit 62 converts the two line-sequential color difference signals into two I
The input and output of the series connection of this IH delay circuit are added, and the added output is set to 1 and taken out to the first and third output terminals, and the IH delay circuit is connected. The configuration is such that the second and fourth output terminals are taken out from the point. The average value of the color difference signals of one of the first and third lines of the three consecutive lines is extracted from the first and third output terminals of the synchronization circuit 62, and the second
The other color difference signal of the th line is taken out to the second and fourth output terminals. Therefore, the synchronized red color difference signal R-Y can be separated by a switch circuit that selects one of the first and second output terminals, and one of the third and fourth output terminals. The switch circuit can separate the synchronized evening color difference signals B-Y.

An ID detection circuit 63 is provided to ensure that the switch circuit of the synchronization circuit 62 operates correctly. I
The D detection circuit 63 detects the ID data added to the record (1.5), and uses this detection to determine the correct phase of the pulse that controls the switch circuit. The two color difference signals taken out from the synchronization circuit 62 are sent to the interpolation circuits 64 and 65.
supplied to These interpolation circuits 64 and 65 interpolate, for example, the average value of two data before and after this data, and the interpolation circuits 64 and 65 output color difference signals RY and RY whose sampling rate has been converted to 4 fsc. B-Y
is obtained. This sampling rate conversion.

This is necessary to achieve the same sampling rate as the digital luminance signal.

The digital color difference signal is provided to hue correction circuit 66. The hue correction circuit 66 adjusts the phase, that is, the hue, of the color signal in which the two color difference signals are combined by changing the values of the two color difference signals.

The color difference signal taken out from the hue correction circuit 66 and the luminance signal from the delay circuit 61 are supplied to a digital matrix circuit 67. The delay circuit 61 is the synchronization circuit 6
The amount of delay is the same as the delay of the color difference signal that occurs between the signal 2 and the input of the matrix circuit 67.

1) Digital 3 taken out from the multiplex circuit 67
The primary color signals are supplied to a color temperature correction circuit 68.

The hue correction circuit 66 and the color temperature correction circuit 68 are also supplied with correction data by a control section 69 consisting of a microprocessor and memory. Data for correction is sent to terminal 10.
specified by control signals from. This control signal C is a digital three primary color signal taken out from the color temperature correction circuit 68 by the operator operating keys and levers while monitoring the hue and color temperature of the monitor image.
It is supplied to converters 72, 73, and 74. Each output terminal 7 of these D/A converters 72, 73, 74
5, 76, and 77, analog component color video signals R, G, and B are taken out. Although not shown, this component color video signal is supplied to an input terminal of a color monitor receiver.

The digital matrix circuit 71 outputs a digital luminance signal and two digital color difference signals that have been corrected for hue and color temperature. The output of this matrix circuit 71 is supplied to a color encoder 78. In connection with color encoder 78, synchronization signal 5YNC
and a synchronization and burst flag generation circuit 79 that generates a burst flag pulse BFP. The output of this color encoder 78 is a digital NTS
The C composite color video signal is taken out, and this composite color video signal is supplied to the D/A converter 46 through the reproduction side terminal of the recording/reproduction changeover switch 15 . A playback signal in the form of an analog composite color video signal is output from the output of the D/A converter 46 to the output terminal 80 through the playback side terminal of the recording/playback switch.

The present invention is applied to the hue correction circuit 66 and color temperature correction circuit 68 described above. An embodiment of the present invention will be described with reference to FIG.

In FIG. 2, reference numerals 90, 91, and 92 indicate input terminals; the input terminal 90 supplies the digital luminance signal Y to the matrix circuit 67, and the input terminal 91 supplies the digital color difference signal R-'Y to the multiplication circuits 93 and 94. The digital color difference signal B-Y is supplied from the input terminal 92 to multiplication circuits 95 and 96. The outputs of multiplier circuits 93 and 95 are supplied to adder circuit 97, and the output of adder circuit 97 is supplied to matrix circuit 67. The outputs of multiplier circuits 94 and 96 are supplied to adder circuit 98, and the output of adder circuit 98 is supplied to matrix circuit 67.

These multiplier circuits 93, 94, 95, 96 and addition circuit 9
7.98 constitutes the Hue correction circuit 66 shown surrounded by a broken line, which includes multiplication circuits 93 to 96 and addition circuits 97.
Hue correction is performed by 98.

In other words, on the color coordinates as shown in Fig. 3, where the horizontal axis is the value of the color difference signal RY and the vertical axis is the value of the color difference signal B-Y,
Color difference signals RY, B- to which vectors shown by solid lines are input
A vector indicating the hue by Y, and this vector is (RY
, BY), the transformation into a vector (R'Y + B'Y) shown by a broken line in which hue is corrected by changing the phase by θ is shown by. Hue correction can be performed by configuring a circuit based on the above equation. By setting the coefficient of the multiplication circuit 93 to cosO, the color difference signal RY supplied from the input terminal 91 is multiplied by cosO, and by setting the coefficient of the multiplication circuit 94 to sinθ, the color difference signal BY supplied from the input terminal 92 is multiplied by cosO. is multiplied by 5if1θ, and the two outputs are combined in an adder circuit 97 to obtain a shiffe-corrected color difference signal R/.

Further, by setting the coefficient of the multiplication circuit 95 to -sin θ, the color difference signal RY supplied from the input terminal 91 is multiplied by -sin θ, and by setting the coefficient of the multiplication circuit 96 to cosO, the color difference signal RY supplied from the input terminal 92 is multiplied by -sin θ. The color difference signal BY is multiplied by cosO, and the two outputs are combined in an adder circuit 98 to obtain hue-corrected color difference signals B and 7.

The correction amount of Hue is determined by the multiplication circuit 93 corresponding to the value of θ,
Coefficients supplied to 94,95.96, cosO,-5i
Determine the size using nθ, sinθ, and cosO. This coefficient is input from terminal 70 to the operator's key.

It corresponds to a control signal supplied by lever operation. The process of multiplying these coefficients corresponding to the hue correction amount can be performed by a look-up table method using a data conversion table calculated by the control unit 69, as will be described later.

The hue-corrected color difference signals R-Y and B-Y output from the adder circuits 97 and 98 are sent to the matrix circuit 6.
7. The matrix circuit 67 performs conversion into three primary color video signals R, G, B, and these three primary color video signals R, G, B are sent to the multiplication circuits 99, 100.
, 101 is supplied with husband.

Multiplying circuits 99, 100, and 101 constitute a color temperature correction circuit 68, which is shown surrounded by a broken line. Gain multiplication circuit 99, 100, 1
Color temperature correction (also called white balance consideration) is performed by changing each coefficient of 01.

The process of multiplying the coefficient for color temperature correction is performed by the control section 6 based on the control signal from the terminal 70, similar to the hue correction.
This can be done by a look-up table method using the data conversion table generated in step 9.

The three primary color component color video signals R', G,
B is supplied to the matrix circuit 71, and D/
It is supplied to A converters 72, 73 and 74. Output terminals 75, 76 of D/A converters 72, 73° 74, respectively
．． 77, analog three primary color video signals R, G
, B are taken out, and these three primary color video signals are supplied to an input terminal of a color monitor receiver (not shown). While viewing the image on the color monitor receiver, a control signal for appropriately performing the hue correction and color temperature correction described above is generated and supplied to the control section 69.

As the multiplication circuits 93, 94, 95, and 96 for multiplying the above-mentioned input data by a predetermined coefficient, those having the following configuration are used.

As shown in FIG. 4, a read or write clock is sent from the control unit 69 to the address selector 111. The data is supplied to the RAM 112 and the data selector 113. The RAM 112 is brought into a read state by a single clock from the control section 69, and brought into a write state by a write clock. The control unit 69 is a CPU
The controller 69 calculates a coefficient sin θ, -5 inch from the control signal, that is, the value of the phase change amount θ, given from the terminal 70 by the operator's key operation.
The values of θ and cos θ are determined, and furthermore, the value obtained by multiplying these coefficients by data is determined, and a data conversion table consisting of these values is formed.

When the write clock is supplied from the control unit 69, the RAM
112 enters a write state, and the write address of the RAM 112 is designated by the control unit 69 via the address selector 111, and the values forming the above-mentioned data conversion table determined by the control unit 69 are written to the RAM 112 via the data selector 113. be included. This updating of data in RAM 112 is performed within the vertical blanking period.

The RAM 112 has addresses of positive polarity values among 8-bit 2's complement values.

When a read clock is supplied from the control unit 69, the RAM
112 is in the read state, and the input data is transferred to the RAM via the polarity inversion circuit 110 and the address selector 111.
112 addresses. The polarity inversion circuit 110 inverts the polarity of input data when the input data has a negative polarity, since the address of the RAM 112 is a 2's complement 8-bit positive polarity value. The output of the polarity inversion circuit 110 is connected to R via the address selector 111.
When supplied to the AM 112, data multiplied by a coefficient of the input data written in advance in the RAM 112 is read out.

The data read into the RAM 112 is supplied to the polarity inversion circuit 114 via the data selector 113. The polarity inverting circuit 114 inverts again the negative polarity input data that was taken out to the RAM 112 as positive polarity data. Data multiplied by a coefficient of the input data is extracted from the polarity inverting circuit 114.

FIG. 5 shows an example of polarity inversion circuits 111 and 115. One sample of carrier color signal is 8-bit data (xQ +
xi + """ + xa + x7), the lower 7 bits are 7 exclusive OR gates 120
゜121.122. ..., 125, 126 are supplied to one input terminal of each. Here, Xo is the MSB
(most significant bit), and X7 is the LSB (least significant bit). Exclusive OR gates 120-126
Xo indicating u MSB is supplied to the other input terminal of
The outputs of these exclusive OR gates 120 to 126 and xO indicating the MSB are supplied to an adder 127. When MSB is 0, data x(,,xl,...X6
．． When X+7 is output as is and -C is extracted, and when MS+3, which indicates negative data based on two's complement, is 1, the lower 7 bits of data XI, X2 . . . x6 . x7 is inverted and L
The polarity is inverted by adding 1 of the MSB to the SB.

[Effects of the Invention] According to the present invention, since it is constituted by a digital circuit, it is possible to realize a color signal correction circuit that has high stability and is easy to integrate into an integrated circuit. Further, according to the present invention, it is possible to realize a gain-tal color signal correction circuit that can control color signals with high precision using a circuit with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a color video signal recording/reproducing circuit to which this invention can be applied, FIG. 2 is a block diagram of an embodiment of this invention, and FIG. 3 is a route diagram used to explain this invention. , FIG. 4 is a block diagram showing a part of an embodiment of the present invention, and FIG. 5 is a block diagram of a polarity inverting circuit according to an embodiment of the present invention. 66... Hue correction circuit, 68...
Color temperature correction circuit, 69...Control unit, 11
2... RAM0 agent Masato Sugiura

Claims (1)

[Scope of Claims] (1) In a digital color signal correction circuit for correcting the hue of the digital color signal, the phase of the color signal on the color coordinates is changed by a predetermined amount according to the first and second color difference signals. and a memory in which the data conversion table is written, and the first and second input gauging color difference signals are supplied as address inputs of the memory. A correction circuit for digital color signals. (2. In the digital color signal correction circuit according to claim 1, a polarity inverting circuit for the first and second input digital color difference signals provided on the address input side of the memory; A digital color signal correction circuit, characterized in that a readout output polarity inverting circuit is provided, and the data conversion table in the memory is related to either positive or negative polarity. (3) Patent The digital color signal correction circuit according to claim 1, wherein the data conversion table generates a phase change amount according to an external control signal, and A digital color signal correction circuit characterized in that the digital color signal is written into the memory within a vertical blanking period of .