JPS6084652A - Access cycle assignment system - Google Patents

Abstract

PURPOSE:To improve an entire throughput by changing an access cycle assigned to an access request origin of a shared storage device temporarily to another access request origin which makes an access request. CONSTITUTION:A control registor group 1 holds control data for N access cycles so as to secure the case of the longest access cycle for the shared storage device 6. A flag 3 which indicates the presence or absence of an access request is used by a processing port determining circuit 4 together with access cycle assignment data 2 when the port to be next accessed to the shared storage device 6 is decided to use actually. This processing port determining circuit 4 changes the access cycle temporarily to another access request origin unless there is access request from an expected access request origin even at an access execution time.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a system in which a high-speed storage device is shared by a plurality of access request sources in a manner in which the devices are periodically accessed based on a predetermined cycle. This is an access cycle allocation method that allows the allocation of access cycles to be dynamically changed according to the generation status of access requests.

Background of the Technology Conventionally, in a method of sharing a storage device by periodically allocating access cycles of one storage device to multiple key sources, the allocation is fixed and the minimum throughput for each request source is guaranteed. .

Prior Art and Problems In the conventional method of periodically allocating the access cycle of one storage device to multiple request sources to share the storage device, the allocation is fixed and the minimum throughput for each request source is On the other hand, there is a drawback that if the number of accesses from a certain request source decreases, the access cycle cannot be used effectively.

Purpose of the Invention In order to eliminate this drawback while guaranteeing the minimum throughput for each access request source, the present invention provides a storage device that is shared when there is no access request from a scheduled access request source even at the access execution time. By temporarily changing the access allocation to one access request source to another access request source, it is possible to improve the throughput of the entire system.The drawings will be described in detail below.

Embodiment of the Invention The figure shows an embodiment of the present invention, in which 1 is a management register group that manages allocation data for each port (access request source) in the access cycle of the shared storage device, and 2 is an access control register in the management register group 1. Cycle allocation data, 3 is a flag indicating whether there is an access request for each port, 4 is a processing boat determination circuit, 5 is a selector, and 6 is a shared storage device. Note that CD indicates cycle allocation, ACN indicates access cycle number, AR indicates access request, ADlo indicates access data/order, and P1 to P4 each indicate a port.

41 in the processing boat determination circuit 4 is an AND gate that takes a bit-by-bit logical product of the access cycle allocation data 2 and the access request display flag 6; 411 is an AND gate 41
42 detects that the output of α110 is α110 and generates a signal 412 notifying the same), and 42 makes a priority judgment between bits set to 1' (that is, between boats) for the access request display flag 6. A priority determination circuit 46 outputs only the highest priority bit, and the output of the priority determination circuit 42 is passed through the α110 signal 412 from the AND gate 411 (α110) + or not (
Not a! 0 ), and 44 is an OR gate that receives data from AND gates 41 and 43 and performs a logical sum.

In the figure, the management register group 1 has the longest access cycle to the shared storage device 6 (one access cycle per N access cycles).
Management data for N access cycles is held in order to guarantee the maximum number of access cycles, and each boat can be configured to access the shared storage device 6 once every N access cycles, up to the longest access cycle. be. Management register group 1
The cycle allocation data 2 within is data that indicates one port (limited to one) allocated by one bit for each access cycle of the shared storage device 6 (1
: Assigned, 0: Not assigned). It is assumed that the setting of cycle allocation data 2 is separately executed using general means using software or hardware. The flag 5 that indicates the presence or absence of an access request indicates the presence or absence of an access request for each boat at the present time (1: Yes, 0: No) for each boat, and indicates the presence or absence of an access request for each boat at the present time, and indicates the next access request to the shared storage device 6. This is used in the processing boat determination circuit 4 together with the cycle allocation data 2 of the access cycle when determining from which port the access cycle is actually performed.

The operation of the processing boat determining circuit 4 will be explained below.

■, Psile allocation data 2 and access request display 7 Lag 6
The AND gate 41 performs a logical product. If the result is not α110, access will not be assigned to the port corresponding to the bit 11n is set, OR
Access from the relevant boat is selected by the selector 5 via the gate 44, and the shared storage device 6 is accessed.

When the output of the AND gate 41 is α110 in (1) and (2), the priority determination circuit 42 performs priority determination between ports regarding the access request display flag 6, and the result is determined by the AND gate 411 and the signal 412. The data is passed through the D gate 43 and input to the selector 5 via the OR gate 44 to select access from the port and access the shared storage device 6.

In (1), (2), and (2), after the access request from the port is processed, the corresponding bit of the access request display flag 60 is reset (the access request flag of the access request source from which the access request was processed is cleared).

In the explanatory diagrams of this embodiment, the number of access request sources (boats) is four, but other numbers can be used in a similar manner.

The present invention is effective when applied to a switching system in which the access cycle of a storage device is used separately for running a program or for buffering data from a transmission line (for example, as disclosed in the previously proposed Japanese Patent Application No. 58-99239). It's thick.

As described in detail of the invention, when there is no access request from the scheduled access request source even at the access execution time, the access cycle allocation to the access request source of the shared storage device is performed. Since the access request source can be temporarily changed to another access request source, it is possible to reduce wasted access cycles of the shared storage device and improve the overall throughput.

[Brief explanation of drawings]

The figure shows an embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Allocation data management register group, 2... Access cycle allocation data, 6... Access request display flag, 4... Processing boat determination circuit, 5... Selector, 6
...Shared storage device, 41,411.43...AND
gate, 412...signal, 42...priority determination circuit,
44...OR Gate Patent Applicant Nippon Telegraph and Telephone Public Corporation Representative Tamamushi Gobe (2 others) −□□−=T bijs / Jun

Claims (1)

[Claims] A flag that displays the presence or absence of an access request from each boat of a plurality of access cycle request sources, a priority determination circuit that determines the priority of the access request source of an access cycle with respect to the flag, and a priority determination circuit that is periodically used by the access request source. In an access cycle allocation method including a shared storage device, a management register group for managing access allocation data for each host that is an access request source of an access cycle of the shared storage device, and bits of the access allocation data and the access request flag. Means for detecting the presence or absence of an allocation Yasugi of the logical product output for each, means for allocating access to the corresponding boat when there is an allocation bag O (as a result of this detection), and means for allocating access to the corresponding boat when there is an allocation request for the detection result a priority determining means for performing a priority determination and outputting only the bit corresponding to the highest priority port; a means for determining whether or not the output from the priority determining means can be passed in accordance with a detection result of said allocated ammonium infinity; and from the priority determining means. and a processing port determination circuit having means for allocating access to a boat corresponding to the passing re-output of the processing port. An access cycle allocation method characterized by temporarily changing and allocating an access cycle to another access request source having an access request.