JPS6076889A - Phase controlling circuit of video signal - Google Patents

Abstract

PURPOSE:To prevent occurrence of false lock in a phase controlling circuit by detecting a phase deviation by using a flag signal and horizontal synchronizing signal and outputting a correction signal of a VCO circuit and a dividing circuit reset signal. CONSTITUTION:When a signal S7 of the VCO circuit 7 causes a phase deviation larger than the width of specified blind sector to a horizontal synchronizing signal HSYNC to be phase-locked, an error signal forming circuit 25 can form an APCID output signal that draws the signal S7 in the signal HSYNC by changing the level of the correction signal S21 sharply. When the phase deviation exceeds an allowable window T2 of operation of a flag signal FG4 for reset signal, a reset circuit 30 resets a dividing circuit 22 by a reset signal RS at timing of rising up of the signal HSYNC.

Description

[Detailed description of the invention]

[1 A, "poor, above field of application"] The invention is applied to the video signal phase tli!I nllll circuit, where 1 = 7.
It is suitable for internal use in the Viteo Tsukugodokoro JIli system (11゛) such as R). ``In the J raw circuit, the color 1 of the color 1'' is locked to the 4R4 raw video signal. Figure 4" lt I 戊のうえうえじ 1 fffljFirst 1
7 times rf1 is used. Ie regenerated from Cheeve! ' The playback low frequency color code number s1 (frequency is) is I
^j In the side conversion circuit 1, 1. ! d The frequency is f after wave number conversion. It is transformed into the carrier color signal S3. The carrier color 1 lucky number S3 that was rejected in this way is ll-1 delayed times west ゛f at the 4th time 11'62 fl of the band pass filter 2.
The output of 3 and the J9- are added to the Sadan circuit to play Song Sending Color 4B.
Sent as @So. This carrier color signal SO is given to the burst sampling circuit 4,
The sampled burst (m signal S4) is applied to the phase comparator circuit 5 and is compared in phase with the output S5 of the crystal oscillator 6 having a cylinder virtual f of the color subcarrier. u5 (z swing 11 (70
0 circuit) is given to 7 and its oscillation rtt=ur6 is an error. - Control the signal S6 in the direction of becoming O. (The output S7 of the VCO circuit 7, which turns on even I4, is given to the 1^j-wave soft circuit 8) together with the output S5 of the 11 oscillator 6, its lI!
The wholesale frequency df of the d mantissa, +f. The carrier signal S8 is sent out. This carrier signal 88 is not applied to the phase shift control circuit 9, is subjected to PI processing by the P/IW signal 89, and is then sent to the frequency speed acceleration circuit 1 as a local signal S2. (Then, the phase of the carrier color 800 is controlled in the phase comparator circuit 5 so that it matches the phase of the output S5 of the oscillator 6 as a reference.
700 circuit 7 which oscillates at sufficiently low frequency &
- Automatic phase control can be carried out easily and safely. However, the above A(1) is obtained by using the output of the vCOu path 7 which is phase controlled based on the berth l extracted from the carrier color signal SO.
2 changes the low frequency color (from M number S1 to hz color sending signal SO
Since a loop is configured to obtain the following, even if a signal with a frequency reduced by 1' from the oscillation 1^+aia of the crystal oscillator 6 is given as a burst signal S4 in this loop, a pseudo-lock state will occur. There is a risk that this may occur. OBJECT OF THE INVENTION The object of the present invention is to prevent such false locking from occurring in a phase control circuit.
It is designed to be adaptable to K. [Oshi of invention! ] In order to achieve this purpose, in the present invention, VCOM
The Atsushi Mari signal obtained by processing the video signal based on the output signal of the signal is processed in the closed circuit section.The flag signal representing the phase within each horizontal synchronization section of the horizontal IDI* signal included in the video No. 48 is processed in the closed circuit section. Using this flag signal and horizontal synchronization signal, it is determined whether the output signal of the 700 circuit has a phase shift of more than a first predetermined portion with respect to the horizontal synchronization section Jv14m for each predetermined horizontal synchronization period. Obtain the pasting signal for 700 circuits, compare the flag signal and the horizontal synchronization signal, detect whether or not a phase shift of the 20th drop foot or more has occurred for each horizontal cycle section, and output the corresponding detection output. The frequency divider circuit B1S is reset by. [Example] An example of the book 'Jl g3 will be described in detail with reference to the drawings below.
Ru. In this embodiment, the phase control circuit includes an APCID circuit 2 in addition to the configuration described above with reference to FIG. This A
PCI l) teoazi playback horizontal JjJi communication 1
It should be followed up by YNC) It should be accepted as a question wave imitation number, and the output of VCU P117 should be followed up by imitation output number S7. The phase of signal S7 is the reproduction horizontal IF'J period signal 118 Y
When compared with the phase of N C, it is in a state where it differs beyond the range to which it belongs, it detects this 11 and generates a signal S2], which is sent to the VCO circuit 7 to oscillate 1+', j his number. Amendment 16
Give it as a number. Here (+) raw horizontal Jtl+ (δ
No. n, '-; yNc is 41) raw from the tape; the horizontal same Jυ included in the No. 16 is sent through the fetch killer circuit to remove the half-etch pulse h: and 1 g is lit. The issue is once a month. APC11J circuit 2] is the 21st g+ VC.
The I#J output signal S7 of the VCO circuit 7 is received by both frequency dividing circuits 22. This frequency dividing circuit 22 is F! The frequency B f, (=378 f□) of the iJ wave Keide no Tsuki No. 6 S7 is divided and the horizontal signal H8YNCa is approximately equal to the period of the month H, which is 1^'' period, which is 1i! ij ll3 power is formed, and in the same section of the first cloth, Figure 3 (support)
As shown in FIG.
A pulse output with a pulse width of 41" corresponding to the 8th frame period is output as a minute output 822, and then in the second branch section, the pulse output is output as shown in Figure 4 (AI). When the pulse of the phantom kushig number S7 reaches 101 Jυ1 minute, the output pulse that corresponds to 411 to the 6th to 10th li'd Jv1 is 1"il-. Output as a divisional output 822, furthermore, invite the first to the third to the 47th, heavy duty + hr r,!it J
In vi, as shown in Fig. 3 (4), the frequency output signal +
The pulse of jS7 causes Ilk' to become 81I! ii Every time Jv 1 minute arrives, the 6th to 8th axes I+! An output pulse of +-r1- corresponding to the pulse 1 per 411 on the d-column is sent out as the branch output 822. Thus, the cylinders Jt and IIIH corresponding to the first period of the horizontal opening 1 signal 1i8YNC are divided into the 1st - 47447th minutes as shown in Figure 5 (1). , the 1st ax, dog', 2'ii+, 3rd to 47th ward 101, 1114 3 evil ω)
, FIG. 4(B), FIG. 3 ω) to the 31st division (13), the pulse 1t! , J B3 forms the force S22. By the way, this means that as shown in Figure 5 (2), the 1st section to the 47th section is 1H, and the 1st section to the 47th section is 1H. '-I
VI47 I'm getting a taste of what it's like to be able to change one song's no result to 1↓ if it's separated by '1'. The border tenth cycle circuit 22 outputs 47 pulses M1 to M47 (
Figure 5 (C1) to (C'47)) on A leg 11h'
＠ and then output i [, which allows l self-voice 1
The member position 16 (therefore the phase) of section 11a is output as a 3rd column A.
The branching circuit 22 outputs the signals in the signal formats i1 to M47 to the decoding circuit. In addition to this, the output output (B No. 87 is divided into 78 + i'il output 523 (for example, pulse M2 /
The output S24 corresponding to 7'L% is applied to the decoding circuit B. When the decoding circuit receives the contents of the output S22 from the output signal S22, the content representing the start and end of the time window tvi 25 T is reached (Fig. 6 [F]).
As shown in FIG. 9, the output from LJ to IJK rises, and then the contents of output 822 represent the rise of MxT. i! 'bury r u
J or [One+1iinJj l-L Error falling on J, ↑II disconnection flag Ff No. 11''G1 occurrence'1-
Ru. This error Hjr HJ flag signal FGI has its rising point I) at 1+1 raw horizontal rotations' (I: I No. 11
sYNc (Fig. 6 (A)) has a specific convergence with the phase of M on the left. I'm late, but I'm a cow 111 times a month. Also, the decoding circuit is horizontal open 1 signal) is YNe's 5) AI Jv,! Every 1/1 hour 511, it emits one error 4i+-output width 1: flag signal 1; This flag signal) G2 is the error mark 1jjr flag No. 16 F'GI rising 11, Naha's eye 11 bond, and the duck j
Month! It has one side of the pulse that becomes I-HJ, and due to this H, when the error detection end flag signal FU2 is h11-filled "1■", the error between the error-1nlljr flag signal II'G1 and the horizontal Jυ1 signal 11sYNc is )11,1 +W,i
Please make sure that the person in charge reads 1 on line 71. Sari 1・'kodecode lj]l f623 is branch output 8
22 timing or 1llr, concentric %l 25 T V
When going up, reduce the force and remove the specified 0) IJ distance Tri
During T I, it is depressed rl (J mustard raccoon "IJ" falls on the insensible firefly setting) 1 (7 lag (-+- No. FG3 is sent. This insensible emperor setting flag signal 1 ゛ G: 3 Hashi, 1 yen! rLJ falling li 4, 1 horizontal ITTI 1 signal H8YNC and error 4'111] ``J (1 flag + fl (G1 How much 4tl I9J's judgment [1] .c2, and thus the starting width of the time window M7S'f is set as ``a fixed direction l111 width is set as an insensitivity 1;''. Flag signal ゛G11) G2, P゛G3 are errors 4M'': Error-41 error flag 1d No. 1I'G2 is given to I every 5B
When rising to fliii+gon "11" during H section (Fig. 6 (B)), playback horizontal direction M, XQH8YNC (fi4
If the rising edge of the error-4q+mr month 1 flag signal FGI occurs after the n++ of the rising edge of the error-4q+mr month 1 flag signal FGI, the previous When it occurs in Il cell 1 (this state DB is horizontal open 1υ1 signal 11S
lI against VNc! (d indicates that the phase of the drumming output signal S7 is delayed) As shown in FIG. 1! If APCIL rises to "H" and sends output information υS20, and outputs output information at the H4 point which is T in response to this, the logic rL rises to "H" as shown in FIG. 6 (F2).
AI'CIDIJ No. 348 826 to become J in 1st year 4
). This It) output signal 826 is APCIl)' tidal current 1. !
26 nl applied to its output 7 and 7 pressure i with capacitor C 11) Output 1
1 L of light to capacitor C when g No. 52() or logic rHJ. 'tli Ba1t vIr, L again t#+? When gon r L J, the current radiated from the capacitor C is L1L'1. Thus, the light of the capacitor C, the voltage V, is as shown in FIG. When the rise of the horizontal Jυ1 11SYNC or the failure of the dead band installation redundant flag signal FG3 occurs at a time point earlier than the section T I, for example, a positive pressure V.2
．． Or just a heavy pressure V. VCO as a correction signal 82 whose level is significantly higher or lower than the signal level of the error signal S6 given from the acquisition circuit 5.
The signal is sent to circuit 7 (FIG. 1). At this time, vCOu path 7 has a 8210' tonnage pressure due to the modification (
Then, the oscillation frequency is controlled to be crystallized stepwise by this amount, and thus the frequency V is output] Month 8+'3S7 Therefore, the phase of error-11fjr flag No. 6i;'Gt is (
'6 Don't let the leaky VC advance 2t, on the contrary, the correction signal 8
lJi of 2J, pressure V. According to this, the talent 1 with low VC
If the output signal S7 of the O circuit 7 is not controlled to be low in steps, the output signal S7 is captured and error-14 occurs.
The phase of the 1-off flag signal FG1 is significantly shifted. 5VC71i:J is set to 1. In this way, the error No. 6 type J Ayu δ is horizontally 1r, and the 51^ of JLI+signal 11SYNC is changed. ” 104 minute section 5
Repeat the phase length determination every 11 times to convert the flag signal FGI for the error width into the horizontal type 4υ1 signal HdoYN.
Let it be pulled into the C phase 4) Like this! Create 19J. The above is error judgment 1 old flag information FGI and horizontally same pitch 4i t+5YNc phase 7 I'm not feeling it because I'm not listening '71
As mentioned above, outside the dead zone '1'1 of the error flag signal +tIL''G3, the i'tL1 error signal is sent from the error signal 4M formation circuit 5, and the I D111 force signal S2ti is sent. , error raw 111τ's January 4 flag - issue 1'G
1 and the horizontal synchronization No. 1 H8YNC become smaller, and when R8YNC's rise or insensitivity/meter setting flag dkii1'G3's insensitivity area + i41 T 1 becomes within 1, The error signal type circuit section is 11)
Output (as shown in Fig. 6 (F3) K as No. g 826 ■
. It sends out a signal to maintain the level J-, and the voltage device is set to 1, 2, and 2 to 2. As shown in FIG. 7, the insensitive output voltage VaoK is maintained, and thus the correction signal 82 is used to maintain the oscillation frequency of the vCO circuit 7 in a normal state so as not to change the oscillation frequency. There is. Therefore, at this time, vCO time j'd7 is the phase comparator circuit 7.
According to the output 86 of
! 7th level■1□, low signal level VL or dead zone 1
tI, the pressure level v (, ov) When the monthly output Kai No. 82 () is sent out, this state is given by the minute 1.ld circuit 22.
t filtration 1iij output. 4M No. 8 will be reset. This central example σ)
Case 1 ^ J Dekai No. 8 S & is 11.1 window M24 T
Due to the rising edge of 1st year 1, it becomes 5th, then ID output (No. 8 S26 is the same wave θ output signal S7 Therefore, error judgment 1 (JR Fukui B No. 1i'G1 phase is horizontal 1+ <l This is due to the fact that it coincides with the JIJ1 signal tlsYNc and is reset 1-before the warping point in the bulge state. In addition to the above configuration, the APCII) circuit 214-1, the Reset circuit: Illustrated 1-1) Set circuit 30 is decode circuit 2: (formed according to ℃ 1i'il 11 power 822 and C), V, Reset Iha issue month 1 flag I as shown in
i' Receive G 4. 7J-11 flag to reset) G4 is the error cliff 4J lv of the divided output 822
At the rising edge of the T Jl'i flux signal FGI (Fig. 6 (B)) A h125 T is 1, and after itl, for example, there are three U, 1 windows.
-7J: Wachi M 22 T ~ M281' 1gl
i=nmi r L J IiC falling operation, 11 to form 1゛2, and other σ) 11 zij river, the signal form becomes logic r ]-1J') 11. In addition to this, the flag signal IL' for reset number 8 is
1'l 2nd occurrence 1-handle] 11 The fifth crotch of the operation permissible window of ``shi'', the cow jibu left ℃・like (iX format is 1
As mentioned above, the decoding circuit 16 receives a total of 824 divided circuit layers. Format σ) 1 Noset information flag Gogo ya4 and horizontal synchronization No. 1 l18γ1゛-
Match 〇 and horizontal do 1 Jui (, '1 hsYN
cσ) Rising or flagging gHt' G4 operational valley HH,
T 2 must be the first theory 'jl 10' It occurred in one person who became HJ, and the reset toy t17lζ8 occurred 1-. As shown in Figure 6 (C1), the horizontal periodic signal 11s
When the rising edge of YNc is in the lH+ state of operation i1-kT2, the reset time ff1i'+:
b) is 51i! Main Ifjl in d period 5 For each if, flag number 1゛G4 or jl, r buried [horizontal 1'J when 11J
JiJ, I Haku 4 Ji 8 SYNC will fall θ,
) generates 67 RS in that city m reset 1 ^ 11 minutes
By resetting the light j'1i22, it is possible to start the °C count based on the rise of the horizontal signal 11 de YNC.

【ing. In this state i/z4, the digit 41-1 of the same temporary o Kushi no Tsuki No. However, 1st hat against 4th output Kai No. 1 S7's 1 standing sum or horizontal rotation "Su・Igi No. if do YI'J"
When the flag 1st number G4 is "1" at the rising edge of the horizontal periodic signal 11S'i'NC from C, the reset circuit 30 is reset to 1θ etc.
J Yul (send S to 22 in each direction and send it to lHj
Chi V this reset, thus water-'l/-IIJJ
JuI 儒gJ-t S Y J~ (Based on jy4, perform various counting operations 1) 1-1 to start 11. Here, the operation of the flag signal FG4 for the reset signal 6'F capacity yt!< Time Φ2 of T2 is horizontal rotation ↓', J11g-a
H, S Y N C and Error Han 11 Dangetsu 4 Flagy R FGI How much is 1 lJ Titeko 11 released 1i' + deviation is 5] -1 time lHl is 11 piece is -1 -1
1 sho of i is enough to stop 1 bu from -4"it above.
r, j K is J cold in advance. For example 'r
ti, the width between each stroke of T2 is set to t9 L' (force), which is slightly smaller than ±0.311 III'IK
Let it smell. In this way #-11 is the horizontal rotation 2H8YNC and the error half 111t1/i Innolag FG1
1, 2j (each J・11 people 1f ko(
If η is doubled so that it decreases by 1, then 1-re(j-water'l'
l'j JI+・(ET -'3 HSYN Cvcj
tte minute'J times kij 12 caricera 1 sai 1. After that, I'll put it in the song of 31i of the 3rd period.
cC'J 51 Uphill: U'il'1'th movement meter T2's IIq
The reset circuit 30 sends the IU input signal n+i'R8 to the branch circuit h''+'I22.・Time 〃"f): JA+ is the dividing time Flt 22 by h・return 5"] and then reset with the 1st vine music. Taking this as a captivity, the phase shift between the force 7 and l11j-Jl [is 5 brackets' Le 5 ratio is 0.5i or more than 7.
The following problems arise. In other words, horizontal parallel 1 signal H8YNC and error judgment) 11
．． 1 When the phase difference from the flag signal 1 size 1 becomes 1011, ri・2
As you can see, the horizontal circuit and Gojitsuki S Y N C start-up switch or plug iy is shown in Figure 6.
The state gl-4K coincides with the falling edge of @F'G 1 . From this state, the position of flag No. 18 FGI is 14, horizontally the same side 11 mm, 7 H8 YNC, the delay is 1, and the advance is an error signal. 8 At the rising edge of YNC, the flux signal FGI is i? +: i + buried “mouth” (sword is 1
i)ii141! r L J ) and t is horizontal J
L, 11 Bakugo 11s YNC's place 41" or go to J' (skill 1 child is advanced) and Qlgrl- Even if you should, do this or Gyaku-Ha instead. become. 11+'iJ for each one that does not let such a shape-maru live.
I had the ability to have a phase that exceeds the motion meter ear window 1゛2 for each section IH of Le I! 1 is used as an enemy and the state of exceeding is obtained. tL j'L is 1/;
-3- In order to prevent the reversal of the position from occurring by resetting the . Thus, with the configuration shown in FIG. 2, the M circuit section 31 is divided into 3#
'Iju, L, Error signal formation circuit station, APC11
J'MillIt, lX2+isden1]-Pig circuit 27
By b positive i No. 6 J Hi formation times h1, 1 support 1s32 is formed 1-ro. In the above 4c/IJM, VC (J circuit 7
Ir, ; 醐rlJi &) f5 is ff1lJ
If it is working in A P c Hot work or 1 palace by doing ell sao, horizontal p5jJU14Q plaster 11
The frequency output signal S7 of the SYNC and vCO circuit 7 is therefore error 4'1. l lf, 1l) 147 Lagui No. 8 FG1
Therefore, the rising edge of the horizontal J4Il signal H8YNC (Fig. 6 (Al)) is the rise of the horizontal J4Il signal H8YNC (Fig. 6 (Al)). Dead zone 1) Occurs between 1 bill l'l, so
The APCID output signal S9 of the error-4F4 forming circuit 5 is '2' as shown in FIG. 6 (F'3). level, and due to this 71, the vehicle pressure of the voltage conversion circuit 27 becomes ■. is the dead band level V. 0 (71st g+) VC9, thus the VCO circuit 7 does not perform any operation to change or correct the frequency of the VCO circuit 7. On the other hand, as shown by the dots in Figure 6 (2), the horizontal synchronization (tf number H8YNC is the flag signal 1 ("G 1
At the time t1 of @++, the logic level of flagging '4rfFGI at this time is rLJ, so the error signal forming circuit 5 outputs KID tA3 as shown in FIG. 6 (Fl). 4i3 issue S 26 level failed! 1F level V. The first signal level is raised to VH, thereby raising the signal level V of the 1+: feedback circuit 27 to the high Ichikawa level V. 8 (Figure 7) Increase K. Therefore, 11 Nen Zhengyu No. 82
1 is vc. The oscillation frequency of the circuit 7 is divided into 1 parts so as to be sieved, and thereby the phase of the frequency output signal S7 and therefore the error-1411 flag No. 4g FGI is determined by 1. In this way, if the rising edge of the horizontal line 113 1iSYNC is insensible (j) and is within the setting flag signal FG3's/iL' + T1, the circuit 6 outputs the error signal form 11) in response to LK. I can't feel the level of 1d No. 826 ■j Level V. (Fig. 6 (F3)) Ic change, or (Vco circuit 7
Terminates the corrective action for. On the other hand, as shown at time t2VC in FIG. 6, the phase of the flag signal FGI is
If 411 of Tl of 1'G3 also deviates from the range, an error occurs according to 7'LK (I3 type JJt circuit 6 is ID output Iha No. 82).
The signal level of 6 is the dead zone 'lFj level V. The lower level e3→5 level vL is lowered to figure 6 (F2)), thus 'City pressure change I kneel down 27? 0: Pressure V. is a low voltage level V. (Fig. 7), the modifier + FS 21 is adjusted so that the fatigue of the VCO circuit 7 is lowered.
Wholesale, this will result in 1 temporary output Tsukudan number S7 Ken is error-4'
1 Tojr flag signal) Interpose the G1 position 'A14 to the horizontal counter 12 No. 11SYNCK. As a result, horizontal opening JiJJ (g+-1jlsYNc O)
Poor rise/? ? If you put in the axis rotation of IT1 for 1 day IT1 in 3's Funosai Tei 1 person for r band installation flag No. 6 J', according to this, error Hakugo Nohi I + lj circuit Z) will be LD output Kai E3 Yoshi S
δ)'s A M level is insensitive/hanging signal and B#V. lci history L (61st case (14゛3)), therefore 1b: pressure conversion circuit V. ib, pressure "Igu Tei City V. rise to 0 (Fig. 7)"
, this corrects the modified signal 'pj 82.1 or VCO circuit 70.
9G swing 1 kun fabric will not be marketed. In this way, the error (8+;- type JJv1 circuit 5 is VCO
If the phase of circuit 7's output signal 887 is 118YNC, the phase of circuit 7 is 118YNC. By significantly increasing the modified signal 8210 level, History 1-II! 1. l Dunhaku Dekai No. 8 S7 horizontally 1”4
A, PCl that seems to draw you into 'Jv1 No. 11 SYNC'
l) Output number 4g can be formed j/1'1, but this phase difference 21 becomes even larger and reset signal flag number 1g FG4 (Dv1 creation in Figure 6 (cl)
1. When the temperature exceeds T2, the reset circuit 3 (
+ is horizontal giant 1 #l (g number H8YN(,' or reset the unknown circuit n at the rising timing and also reset it by number l y S. It is this time % lt. Based on the same number Ng number 11sYNc, the branching operation of the report output 1 @ number 87 will be started again.
Thus, in the error signal form l, the place 1'1 in 52b is
．． -1 of l shift: 1l11. I'm going to do it properly with 11 and 11 fathers. On the other hand, if fL is small and horizontally the same, 1 information 11sY1' VIc is d++1, rF Yonrei 1'2, with a door that does not exceed one pond wall, horizontal 1'? J period A No. 6 11 Do Y
NC's 51i! It is reset every time of 1-1, that is, 5fi.
Since & is not provided, the reset circuit 30 generates the set signal R8 in response to the rise of the horizontal parallel trace 1d 118YNC which occurs at this time, thereby making it possible to reset the frequency dividing circuit 2t. In this way, the frequency divider circuit 22 is reset at the timing of the horizontal synchronizing signal 11SYNC every 5 cycles υ1, that is, every 5H, and starts a new minute JriILψ1 operation. ``This will occur.'' Osugi 1 will perform the detection operation at that point. In this way, the position + of the above-mentioned 1j brother VCO circuit 7 JJQ number output number 17 S7 is 4 times larger than that of the horizontal rotation Jv: Ibariwa 118Y to C. 11. This is the correction signal S21 of the signal level 1 to correct this.
It is possible to feed the VCO circuit 7 from the PCIIJ circuit 21, thus converting the VCO circuit 7 to the horizontal line 1();
It is possible to change the state of YNC No. 4111 Ctj to 19 U Kashiwara. Therefore, the example is VTI this 03',
7A! vCO circuit 7 in the erect animal as at the time of injection.
Launch of Zhou Kunei and Horizontal I "" 1 Le 11b, 1i8YNC
o,) Zhou Diei and @! 91-Nino! Even in the case of μ, ゛1, which is already higher than
vCO1 based on 6 K! ,! Control circuit 7 tall -
3-ru A P Cmu yarn production is horizontal jυ' (if I
Ii can be effectively turned M when the valve, C-like lock is applied to other than Il J S Y N C. As mentioned above, Honmoto Akinyono 1 is included in the APCI stone thread.
nru vCO rotation 0 允 下 朲敲 The power signal's slope number Therefore, the phase should be locked In the commission, I was able to force the young man into a lock-like gauze, and then the next level was 48 r't, but whether or not it was! rll
When the phase shift becomes equal to or greater than the constant L1 when l# is 1 - VC (J IL! l path circumference) Divide the frequency of the j signal. Same as above. Reset fl. “The resultant force, No. 1 + #, was created by making the 11-n bill 1
r can be made into one piece by Il'+71Jt.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the mN1tll configuration of the VITEO (8B phase control at one time and 6 hits per turn) circuit. 31pl-Figure 5 shows the benefit 1 of the configuration of the frequency divider circuit.
ni 1 (signal waveform diagram, No. 61 ￥ 1 (・Ma 21 ♂ 2 diagram σ)) Each 81. signal is not shown.
1￥1 is: (', TI7 in Figure 2. This is a curve diagram showing the output signal of the voltage converter circuit.
...APCI L) circuit, 22, 24... Frequency divider circuit, 2:3... Tecode circuit, N5-1 Rai 6±4
Shape, time r6.2 (i-APC11)'hei, ura σ1.2
7...71→, pressure transfer circuit, 30...reset circuit 1
, 31...min) h'' circuit part, :32...i (4 true information code formation circuit 61...

Claims (1)

[Claims] Processing the video signal based on the output signal of the vCOH path
The phase of the obtained frequency signal is compared with the phase of the reference same wave number signal in a phase comparison circuit, and based on the comparison result, the phase of the output signal of the 700 circuit is locked to the upper mlh forward direction wave number. The phase control of the video signal made (in the oil circuit, (al) each horizontal 1 of the horizontal synchronization number 4N included in the video signal by dividing the above frequency signal) = I JIJI 12 positions, Representing 11J - sending out the flag code + 1'6 times '0 capital', (1)) The above flag part number and 上0已水31 (using the number 4 and 1 Buddha name) Horizontal IU-I JtJ of Ph5i'-
1 section and K Output 4 of above V COMal l+'6
1st IJt for No. 8 or upper ML horizontal same J Su 1 I
Detecting whether or not there is a phase shift over a rectangular product and performing the above 700
a correction signal forming circuit section for sending a 1-positive signal to the circuit; (c) the flag signal and the water Xr'-1#I J;
Compare the j71 signals and find the phase greater than or equal to the second W +
Each horizontal opening JIJ: L, ! 81'F
In particular, the phase control circuit of Video No. 451 is designed to share the following with a reset circuit that outputs 6 and sends the 4/11 output as a reset signal to the above-mentioned circuit section.