JPS6070837A - Speed converting system - Google Patents

Abstract

PURPOSE:To economize the speed conversion by applying envelope length conversion to a bearer speed signal of 3.2kb/s of (6+2) envelope form into the (6+4) form to convert the signal into an 8kb/s speed signal after the said bearer speed signal is converted into a 6.4kb/s speed signal. CONSTITUTION:The (6+2) envelope signal having 3.2kb/s bearer speed is converted into the 6.4kb/s speed by means of envelope repetition. Then the synchronizing bit F of 6.4kb/s speed signal is expanded into 3 bits F0, F1, F2 and converted into the (6+4) envelope signal, a speed signal of 8kb/s is obtained. The synchronizing bits F0, F1, F2 play a role of the same function as that changed in 0.8k times/s in the same manner as the synchronizing bit of the 6.4kb/s speed signal. The (6+4) envelope signal of 8kb/s speed is converted into the 64kb/s speed signal by repeating each bit 8 times. Thus, the interface to the 64kb/s digital conversion of 8k frames/s X8 bits is attained in this way.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides (6+2) envelope format + 7) 3.2k
The present invention relates to a speed conversion method for uniformly converting a b/s bearer speed signal to a 64 kb/s speed signal using the same method as a 6.4 kb/s bearer speed signal, and for inversely converting the same.

[Background of the invention]

Conventional speed conversion schemes of this kind include - as an example.

A 5.2 kb/s bearer speed signal in (6 + 2) envelope format is converted to 4 kb/s by envelope length conversion from (6 + 2) to (6 + 4), and then 64 kb/s by 16-bit repetition. There is a method that performs speed conversion to s.

However, such a conventional method is 64kb/
Since the speed conversion rule is different from the speed conversion rule for s, it is necessary to install a speed conversion circuit for each speed in exchanges handling various speed classes, which is complicated and uneconomical.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to
．． 3.2 kb in the same way as the 4 kb/s bearer speed signal
An object of the present invention is to provide a simple and economical speed conversion method capable of mutually converting a 64 kb/s hair speed signal and a 64 kb/s signal.

[Summary of the invention]

The configuration of the speed conversion method according to the present invention converts a 5.2 kb/s bearer speed signal in a (6+2) envelope format into a (6 +
2) 6.4 kb/by envelope repetition
After converting to s speed signal, (6+2) to (6+4)
By performing envelope length conversion to 8
Convert to kb/s speed signal and further bitwise 8
Convert to a 64 kb/s speed signal repeatedly, or inversely convert the above.

The process converts the 64kb/s speed signal into a 5.2kb/s bearer speed signal.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 1 is a block diagram of an embodiment of a digital data exchange network to which a rate conversion method according to the present invention is applied.

Here, the digital data terminal DDTE is 64kb/
In order to connect to the digital data exchange DDK via the time division digital exchange TDX, a digital data exchange connection device DXCE and a 64 kb/s digital exchange subscriber control device DSCIli are newly installed.

The digital data terminal DDTEK is available with various bearer speeds, and the 64 kb/s digital switching subscriber controller DSCE converts such multiple bearer speeds to the standard speed of the digital data switching network, 64 kb/s, and I am trying to do the reverse conversion.

There are various types of multi-bearer speed signals, among which a 3.2 kb/s bearer speed signal in a (6+2) envelope format is used for mutual conversion with a 64 kb/S speed signal. It was said that the speed conversion rules were particularly different compared to other types, making it difficult to treat them in a unified manner.

In the present invention.

64 above. kb/s digital subscriber controller DSCB
We are trying to solve this problem.

Below, the above 64kb/s model The speed conversion in the station DSCE will be explained.

FIG. 2 is a conversion format diagram of a speed conversion method according to the present invention, and FIG. 5 is a block diagram of an embodiment of the speed conversion circuit.

Here, 1.2 is the envelope synchronization detection circuit (FDET
), 5 and 4 are serial-to-parallel conversion circuits (SP); 5.6 is a synchronous pattern generation circuit (FG); 7 and 8 are parallel-to-serial conversion circuits (PS); and 9.10 is a flip-flop (FF).

First, the basic principle of speed conversion will be explained based on FIG.

This figure shows an example in which an envelope format is constructed with 6 bits of data (Do = Ds) and 2 bits of synchronous 0° signal (S).

As a first step of speed conversion, a (6+2) envelope signal with a bearer speed of 5.2 kb/s is converted to a speed of 6.4 kb/s by repeating the envelope.

As a second step, the synchronization bit F of the 6.4 kb/s speed signal is expanded to 5 bits (FOlFl, F2).

(6+4) Convert to envelope signal. This results in a signal at a speed of 8 kb/s. here.

Synchronization bit FO, F1. F5 is the same as the synchronization bit F in the 6.4 kb/s speed signal, changed by 0.8 times/s, and can perform the same function.

As a third step, the (6+4) envelope signal at a rate of 8kb/s is repeated 8 times to produce 64kb/s.
& Convert to speed signal.

With the above, 8 frames/s x 8 pits of 64
It becomes possible to realize an interface to the kb/S digital exchange.

Note that when returning from 64 kb/s to 5.2 kb/S bearer speed, it can be similarly achieved by performing the above-mentioned inverse conversion.

Next, the operation of the speed conversion circuit will be explained based on FIG. 5, and this circuit is necessary in the 64 kb/S digital switching subscriber control unit DSCE shown in FIG.

First, from 3.2kb/S bare 2 speed signal to 64kb/S
Conversion to a speed signal will be explained.

The envelope synchronization detection circuit 1 receives the input 5.2 kb.
/S Detects synchronization pattern from serial data, synchronization clock 0.8kHz, 3.2kHz, 8k)lz
is supplied to each section described later.

The serial/parallel conversion circuit 5 converts the input 3.2 kb/S serial data into parallel data according to the 3.2 kHz synchronization clock.

The synchronization pattern generation circuit 5 uses the synchronization clock 0.8k.
Hz, a synchronization pattern with a speed of 0.8 kHz and a number of bits of 3 (input data is 1 bit) is generated.

When the parallel data and synchronization pattern are input, the parallel-to-serial conversion circuit 7 performs speed conversion and envelope length conversion in accordance with the synchronization clock of 0.8 kHz to 8 kHz, and outputs serial data at a desired speed of 64 kb/s. .

This data is retimed by the flip-flop 9 and sent out as a converted output.

Then % 64kb/fi speed signal to 5.2kb/
Conversion to an s bearer speed signal will be explained.

In the 64kb/S serial data, the same bit is repeated every 8 pits, so only one arbitrary bit is detected by the envelope synchronization detection circuit 2. It is taken into the serial/parallel conversion circuit 4.

The envelope synchronization detection circuit 2 detects the frame pattern F from the 64 kb/S data using a bit string sampled at 8 kHz. , Fl, and F2, and outputs a synchronized clock of 0.4kHz. It also outputs a synchronous clock of 3.2 kHz corresponding to the signal speed.

The data stored in the serial/parallel conversion circuit 4 and the synchronization bit F generated by the synchronization pattern generation circuit 6 are set in parallel in the parallel/serial conversion circuit 8 in accordance with the synchronization clock of 0.4 kHz. In other words, the parallel-to-serial conversion circuit 8 has o4
kHz4kHz.

Do, D4. D2. D5. D4. D5. Data is set in the order of S.

This data is sequentially read out with a 5.2 kHz clock, retimed in flip-flop 10, and then
．． Sent as a converted output of 2 kb/s data.

In this way, any of the speed conversions described above can be realized economically with a simple circuit configuration.

[Effects of the Invention] As described above in detail, according to the present invention, mutual conversion between a multi-bearer speed and a 64 kb/s speed is possible at a speed of 64 kb/s.
/s is the basic clock rate of the digitally switched network.
kb/s X n (n = 1 + 2 + 4.
8), a remarkable effect can be obtained in economicalization and simplification of this type of speed conversion.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of a digital data exchange network to which the speed conversion method according to the present invention is applied, FIG. 2 is a conversion format diagram of the speed conversion method according to the present invention, and FIG. FIG. 2 is a block diagram of an embodiment of the speed conversion circuit. 1.2...Envelope synchronization detection circuit% 6,41.
, serial-parallel conversion circuit, 5, 6... synchronous turn generation circuit, 7.8... parallel-serial conversion circuit, 9.10... flip-flop.躬 l Figure - Multidimensional Arara 1 L (4#b15 64Kb Hiko Uni/X
-Monkey Figure 2

Claims (1)

[Claims] t (6+2)-r-envelope format 3.2kb/s
After converting the bearer speed signal into a 6.4scb,'s speed signal by (6+2) envelope repetitions,
+2) to (6+4), converting it into an 8 kb/s speed signal, and then converting it into a 64 kb/s speed signal by repeating it bit by bit 8 times, or by performing the above inverse conversion process. 64kb/s
A speed conversion method that converts the speed signal into the 32 kb/s bearer speed signal.