JPS6069940A - Data reception system - Google Patents

Abstract

PURPOSE:To attain data reception via each data communication line without waiting time by selecting alternately two data communication lines every time data for one block's share is transmitted. CONSTITUTION:When a data communication request signal RQ2 is applied from other data processor during the reception where a channel CH1 of a data communication line is used, the signal RQ2 is fed to an AND circuit 7 via a receiver 6b. A data communication interface IF2 is finished for the reception of reception data RD1 for one block's share of the CH1 and outputs a reception data preparation signal RP, this is fed to an FF4 as a trigger signal via the circuit 7 and enable-signals EN1, EN2 go respectively to logical H and L. Thus, gate circuits 3a, 3b are made inoperative and operative respectively and after a data processor 1 reads the data RD1, a data signal permission signal AK outputted from the IF2 is outputted to a CH2 as a signal AK2 via a circuit 3b and a driver 5b. The CH1 and CH2 transmit data of each one block alternately without waiting time in this way.

Description

[Detailed description of the invention] [Technical field] The present invention relates to a data reception system.

[Prior Art] One of the data communication methods is that the transmitting side sends out a data communication request signal requesting the use of a data communication line, and the receiving side returns a data communication permission signal permitting use of the data communication line. Therefore, there is a data communication method in which the state of the data communication line is checked in advance before data is sent and received.

In this data communication system, only one data communication line can be constantly connected to one data communication interface. For this reason, when it becomes necessary to receive data using another channel, conventionally, after data reception on channel 1 is completed, the connection is made to the other channel and data reception from the other channel is performed. was. However, this conventional system has the disadvantage that (1) when data reception on the channel side takes a long time, other channels are forced to wait for a long time.

[Objective] It is an object of the present invention to eliminate the drawbacks of the prior art described above and to provide a data reception method with no waiting time by allowing both channels to receive data in parallel.

[Configuration] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a data communication ffl device according to an embodiment of the present invention.

In the figure, 1 is a data processing device that performs various processes on data, 2 is a data communication interface for the data processing device 1 to communicate via a data communication line, and 3a
and 3b is a gate circuit for switchingly connecting the data communication interface 2 to either channel Cl1l or channel CI+2 of the data communication line; 4 is a gate circuit 3a;
, '3b are activated. Enable signals ENI, EN
This is a flip-flop that generates 2.

5a is a driver that outputs transmission data SD and a communication control signal (data communication permission signal AKI when receiving) to channel C old; 6a is a communication control signal added from channel Cl1l (data communication request signal nQ1 when receiving) and received data. a receiver that outputs RDL to the gate circuit 3a, 5
b is a driver that outputs a data communication permission signal AK2 to channel C112, and 6b is a receiver that outputs data communication request signal 1 (Q2 and received data 1 mark 2 added from channel c112 to goo1-circuit 3b).

In the configuration described above, the data processing device l normally uses channel C.
111 to exchange data with a corresponding data processing device (not shown). Data reception via channel C112 is performed only when data is transmitted from another data processing device via channel Cl12 while data is being transmitted from the other party via channel Cl11.

First, the operation during normal reception will be explained.

In a normal state, the flip-flop 4 is reset, and therefore the enable signal becomes the logic level rLJ (see FIG. 2(c)), and the gate circuit 3a is placed in an operable state.

In this state, when a data communication request signal RQI is applied from the other device via channel C old as shown in FIG. Notice. At this time, if the data processing device 1 is in a state where the received data can be processed (for example, transferred to a storage device), it returns a receive enable command to the data communication interface 2, and as a result, the data communication permission signal AKI is sent from the driver 5a to the channel. Output to C111 J-
L (see Figure 2(b)).

The other party's device receives the data communication permission signal AKI.

One block of data consisting of a predetermined number of bits is output to channel C111 of the data communication line, which receives the received data R.
The data is received as DI by the data communication interface 2 as shown in FIG. 2(d).

Upon receiving one block of data RDI, the data communication interface 2 outputs a reception data preparation signal RR (see FIG. 2(e)), and informs the data processing device 1 that one block of reception data has been accumulated. Notice.

The data processing device 1 that receives this reads one block of received data RDI via the data communication interface 2, and transfers this received data RDI to, for example, an auxiliary storage device.

Such operations are repeated for each block of received data RDI, and the data transmitted from the other party's device is input to the data processing device 1.

Next, a case will be described in which data is received in parallel from channels C111 and C112 of the data communication line.

When reception using the channel Cl11 of the data communication line is performed as described above, if a data communication request signal It02 from another data processing device is added at the timing shown in FIG. 3(f), for example, This data communication request signal 1 (port 2) is applied to the AND circuit 7 via the receiver 6b.

After this, the data communication interface 2
When the reception of the received data 1<Dl is completed and the reception data preparation signal RR is output, this signal RR is applied to the flip-flop 4 via the AND circuit 7 as a trigger signal TR (see FIG. 3(g)). . As a result, the state of the flip-flop 4 is inverted, and the enable signal ENI becomes the logic level "old", and at the same time, the enable signal CI, 1
2 becomes the logic level rLJ.

Therefore, the game I circuit 3a is rendered inactive and the goo 1 circuit 3b is rendered operational, and after the data processing device 1 has read the received data RDI, the data communication interface 2 outputs the data. The permission signal is outputted to channel CH2 as data communication permission signal AK2 (see FIG. 3(i)) via gate circuit 3b and driver 5b.

As a result, the data communication interface 2 receives one block of received data R, D 2 (see FIG. 3(j)) output from the data processing device connected to the channel CH2.

When reception of one block of received data RD2 is completed,
The data communication interface 2 receives a reception data preparation signal R.
Output R. As a result, the trigger signal TR is applied to the flip-flop 4 in the same manner as described above, and its state is inverted, the enable signal ENI goes to the logic level rLJ, and the enable signal sum η goes to the logic level. In the operating state, the gate circuit 3b becomes inactive.

As a result, channel C old is selected and received data RDI
is received.

Furthermore, the flip-flop 4 is triggered again by the reception data preparation signal RR output after one block of this reception data RDI has been received, and this causes the channel CI! 2 is selected.

The above operation is repeated while the data communication request signal RQ2 is applied from the channel CH2, thereby causing the received data I? DI and RD2 are alternately received by the data communication interface 2 and input to the data processing device 1. Then, when the data communication request signal RQ2 falls after the last data RD2 is transmitted, the AND circuit 7 becomes inactive, and since the gate circuit 3a is in the operating state at this time, the initial state is , and communication is performed on the old channel C.

Note that the trigger signal TR is also applied to the data processing device 1, and is used as a signal for distinguishing between the received data RDI and RD2).

[Effects] As explained above, according to the present invention, two data communication lines are alternately selected each time one block of data is transmitted, so data can be transmitted via each data communication line without waiting time. data can be received.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a device according to an embodiment of the present invention, FIGS. 2(a) to (e) are waveform diagrams showing normal operating conditions, and FIGS. 3(a) to (j) is a waveform diagram showing a reception state when a pass request is received from another channel. DESCRIPTION OF SYMBOLS 1... Data processing device, 2... Data communication interface, 3a, 3b... Gate circuit, 4... Flip-flop, 5a, 5b... Driver, 6a
, 6b... Receiver, 7... AND circuit, Cl1
l, CH2...channel.

Claims (1)

[Claims] In the data reception method, when a data communication request signal requesting the use of a data communication line is sent, a data communication permission signal is sent to permit the use of the data communication line and the data is received. It is connected to a data communication interface via a gate circuit, and when a data communication request signal is sent from another data communication line while data is being received via one data communication line, the gate is connected to the data communication interface every time one block of data is received. A data reception method characterized in that one block of data is alternately received via two data communication lines by switching circuits and alternately sending data communication permission signals to two data communication lines.