JPS6069909A - Automatic channel selecting device - Google Patents

Abstract

PURPOSE:To realize quick automatic channel selection by discriminating whether a received frequency is near a broadcast frequency or not and operating an amplifier circuit and a counter circuit only when it is discriminated that the received frequency is near the broadcast signal frequency so as to improve the accuracy of the stop of automatic channel selection. CONSTITUTION:The discrimination of a station near signal is performed and only when the received frequency is near the broadcast signal frequency, an intermediate frequency fIF is amplified 14 so as to discriminate accurately the station near signal thereby improving the accuracy of the stop of the automatic channel selection. Moreover, the counting operation of the counter circuit 15 is conducted only when it is discriminated that the signal is near the station, thereby changing a channel instantly without counting when the signal is not the station near signal, and then quick automatic channel selection is realized and also the count time is taken longer.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an electronic tuning receiver including a PLL frequency synthesizer, that is, an automatic tuning device for a PLL receiver.

(b) Prior art In general, in a PLL receiver, from the intermediate frequency stage of an AM receiver, the characteristics shown in Fig. 1 are obtained when a narrowband filter is used, and when the narrowband filter is not used. A signal meter driving output having the characteristics shown in FIG. 2 is outputted, and a band meeting signal obtained from the S-curve signal is outputted from the detection stage of the FM receiver. As is clear from FIGS. 1 to 3, the signal meter drive output and the band muting signal indicating the signal strength of the intermediate frequency are at the center frequency f of the intermediate frequency. Since the detuning frequency △f from Conventionally, automatic channel selection has been stopped in accordance with the determination result of a nearby station signal such as a signal meter drive output or a band muting signal.

However, near-office signals such as signal meter drive output and band meeting signals are
Since the bandwidth is not very narrow, IKHz is used with AM receivers.
If you want to perform automatic tuning every step, or every 25KHz to 50KHz step with an FM receiver,
It has been difficult to stop automatic channel selection by determining these nearby station signals.

Therefore, recently, in addition to the determination circuit that determines the near-station signal, a counting circuit that counts intermediate frequency signals and a determination circuit that determines whether the count value of this counting circuit is within a predetermined range have been provided. A method has been adopted in which automatic channel selection is stopped using an AND signal of the outputs of both decision circuits. Here, when counting intermediate frequency signals, especially in AM broadcasting,
Since the intermediate frequency signal is amplitude modulated, it is necessary to amplify the intermediate frequency signal and apply it to the counting circuit, but if the intermediate frequency signal is constantly amplified, interference will occur due to harmonics of the intermediate frequency signal. There was a problem that the reception condition deteriorated. For this reason, conventionally, the audio muting signal output from the receiver's control circuit during channel selection is used to mute the audio muting signal.
The intermediate frequency signal is amplified only during the period when the timing signal is output.

However, in such a method, since the intermediate frequency signal is amplified even when determining the near-office signal, there is a drawback that harmonics of the intermediate frequency signal cause malfunctions in determining the near-office signal. In addition, since the counting circuit must be operated all the time, the counting time cannot be taken too long, and the noise generated from the counting circuit is
There was a problem that it had a negative effect on L. Furthermore, since the automatic channel selection is stopped by the AND signal of both decision circuits, counting is performed even when the station is not near the station after the channel is changed, resulting in a disadvantage that the channel selection time becomes longer.

(c) Purpose of the Invention The present invention aims to stop automatic tuning with high precision at the optimum reception point even when automatic chest selection is performed in small frequency steps, and to realize quick automatic tuning. In addition, it is designed to suppress as much as possible the negative effects such as a decrease in the power density due to the amplification and counting operations of the intermediate frequency signal.

(2) Embodiment FIG. 4 is a block diagram showing an FM receiver which is an embodiment of the present invention, (1) is a receiving antenna, (2) is a mixer, (3) is an intermediate frequency amplification circuit, ( 4) is a detection circuit, (5
) is a low frequency amplifier circuit, and (6) is a speaker. or,(
The sword has a crystal oscillator (8) and a reference divider (
9), programmable divider α0), phase comparator <
If), this is a PLL frequency synthesizer composed of a low-pass filter 021 and a voltage-controlled oscillator Q31 as a local oscillator, and the channel is changed by changing the frequency division number of the programmable divider (10).

Furthermore, in FIG. 4, a4 is an amplifier circuit that amplifies the intermediate frequency signal f□0, α is a counter that counts the amplified intermediate frequency signal f□, and (16) is a timing signal TS that determines the counting time. In order to detect whether or not the generated timing generator (I7) and 0 town count value are within a predetermined range from the lower limit value N, , to the upper limit value NH, the output of the counter α is input, and the lower limit value and A lower limit detection circuit and an upper limit detection circuit that output detection signals LF and HF when the upper limit is reached, respectively, an RS flip-flop that is set and reset by α dark detection signals LP and HF, and (20) a timing signal. TS is input to the clock terminal CL, and its flip-flop (Q of 19) is input.
D flip-flop whose output is input to the data terminal, C
υ is the search switch to start auto search, (
2 is a control circuit that controls each part, c! J is NAND
Gates (24) and (25) are inverters.

FIG. 5 is a flowchart showing the functions of the control circuit (c), and the operation of this embodiment will be described below with reference to this flowchart and the timing chart of FIG.

First, when the search switch Qυ is pressed to start the auto search, the signal SW changes to "H" as shown in Figure 6 (a).
”. When the signal SW becomes "I("), the control circuit (company) changes the audio meeting signal A-MUTE to "IIJ".
(Fig. 6)), and by changing the number of divisions of the programmable divider θQ, the channel CH
from A to B, and change the reception frequency (6th
Figure (b)). Then, after changing the channel, for a certain period of time T,
After the lapse of time, the band meeting signal M (Fig. 6 (c)) obtained from the detection stage is judged (see Fig. 6).
'rMl).

In Fig. 6, even if the channel CH is changed from A to B, the band meeting signal M is rHJ, that is, it is not near the station, so it is immediately transferred to the next channel C without performing amplification and counting operations. After the change, the band muting signal M is judged again. In this way, the channel change and the post-change determination are performed once and for all.

For example, if the band muting signal M changes from rHJ to rLJ after changing the channel CH from D to E, the determination after the channel change is that rLJ
The level band meeting signal M is determined, and it is found that the receiving frequency is close to the broadcast signal frequency. Therefore, the control circuit (2) uses a predetermined period signal STRQ (Fig. 6 (H)
) is set as "H". When the signal 5TRQ becomes [I-(j), the amplifier circuit starts amplifying the intermediate frequency signal f□.The amplified intermediate frequency signal ffF becomes the signal 5TILQ as shown in FIG. Counter α9 only during rHJ period
will be applied. Also, the timing generator (16) and the D-flip 70 set are released, and the timing generator (1G) begins to generate a timing signal TS that determines the count time T3 (FIG. 6 (g)). Reset terminal R of counter (15)
is a NAND gate (
Since the output of (c) is input, the counter (i5) counts the amplified intermediate frequency signal f,7 for a count time T determined by the timing signal TS.

Here, if the reception frequency is not the optimal reception point (, counter (
Assuming that one count value reaches the lower limit value N, , within time 13, and also reaches the upper limit value NH, first, the detection signal LF is output from the lower limit value detection circuit α7) (see FIG. (G)), as a result, the RS flip-flop (19) is set, but the detection signal HF of the upper limit value detection circuit a is also output (Fig. 6 (January)).
Since the signal H is reset, the D input of the D flip-flop (2@) becomes rLJ. Therefore, at the falling edge of the timing signal TS, the D flip-flop (4)
The Q output remains rLJ and does not change, and the stop signal 5TOP
is not output and remains rLJ.

The control circuit (2) outputs the stop signal 5T when a time T equal to or longer than the count time T3 elapses after outputting the signal 5TRQ.
OP is determined (TM2 in FIG. 6), and if rLJ, the channel CH is further changed from E to F. Then, in the same way as described above, the band meeting signal M is judged, and if rLJ, the signal 5TRQ is generated, and the amplifier circuit (
14) and counter a9 are operated. Note that after the channel CH is changed from E to F, the signal 5TRQ remains at the rLJ level until the band muting signal M is determined, so the amplifier circuit (141 and counter haze) do not operate.

In this case, the received frequency enters the optimal tuning point and the counter (
If the count value of 151 reaches the lower limit value NL within time 13 but does not reach the upper limit value N9, the detection signal LF is output from the lower limit value detection circuit output, but the detection signal LF is output from the upper limit value detection circuit ua. Since the signal HF is not output, R
The S flip-flop 9 remains set. Therefore, at the falling edge of the timing signal TS, D
The flip-flop (to) changes to rHJ, and a stop signal 5TOP is output as shown in FIG. 6 (nu). The control circuit @ determines that the stop signal S'I' OP is "H" when a predetermined period of time {r2} has elapsed after outputting the signal 5TRQ, and therefore stops the channel change and stops the auto search.

After that, the audio muting signal A-MUTE is rLJ
The sound of the selected broadcasting station will be heard from the speaker (
6). In addition, time T.

As a result of counting, if the count value does not even reach the lower limit value N, , the detection signals LF and HF are not output, so the stop signal 5TOP is not generated. That is, the stop signal 5TOP is generated only when the count value falls within a predetermined range from the lower limit value NL to the upper limit value N3.

In the above embodiment, after changing the channel CH from E to F, the band matching and jL-ting signal M are judged. This is to prevent malfunction, and the channel CH is changed from D to E. Since it has already been determined that the location is near the station when the change is made, it may be omitted.

By the way, in the present invention, when the count value at count time T3 is within a predetermined range, it is determined that the optimum tuning point is reached, but in reality, this predetermined range is, for example, 10.7 MHz in the FM band. ±l0KHz, 450K in LW band
Hz±0.6K Ilz, 450KH in MW band
It is sufficient to set it as z±3K11z. In this case, if the count time T is 12 Q 7FLSec, the upper limit N,
and the lower limit NL is NFI=4128520 in the FW band.
0J, NL=[282800J, I'L+ in LW band
= r 54072 J, NL = "53928 J, MW
In the belt, N, I = "54360J, NL = "53640J
becomes.

In addition, although the FM receiver was explained above,
It is also applicable to M receivers, and the signal meter drive output obtained from the intermediate frequency stage may be used instead of the band muting signal as the near-station signal.

Effects of the Invention The present invention makes it possible to accurately determine the signal near the station and amplify the intermediate frequency signal only when the receiving frequency is near the broadcast signal frequency. The accuracy of automatic tuning and stopping will improve. In addition, since the counting operation is performed only when it is determined that the station is near, there is no need to count when the station is not near the station. This makes it possible to realize a station and increase the counting time.

Furthermore, since the amplification circuit and the counting circuit that amplify the intermediate frequency signal are operated only for a predetermined time when necessary, it is possible to minimize the negative effects such as a decrease in analogy that accompanies the amplification and counting operations. .

[Brief explanation of drawings]

1 and 2 are characteristic diagrams showing the characteristics of the signal meter drive output, FIG. 3 is a characteristic diagram showing the characteristics of the band muting signal, and FIG. 4 is a block diagram showing the embodiment of the present invention,
FIG. 5 is a flowchart showing the functions of the control circuit, and FIG. 6 is a timing chart for explaining the operation of the embodiment shown in FIG. Explanation of main drawing numbers (3)...Intermediate frequency amplification circuit, (4)...Detection circuit, (Katana...PLL frequency synthesizer, 00)
・Programmer pull divider, αJ ・Voltage controlled oscillator, (14) ・Amplifier circuit, α dynamic ・Counter, a cap ・Timing generator, aη ・Lower limit value detection circuit, U ・ Upper limit Value detection circuit, αω...
・RS flip-flop, CI'0)-D flip-flop, (2υ...Search switch, Co., Ltd....Control circuit. Figure 1 Figure 2 Figure 3 <f IlkHz)

Claims (1)

[Claims] (1) An amplifier circuit that amplifies an intermediate frequency signal and a counting circuit that counts the amplified intermediate frequency signal, and when the count value of the counting circuit is within a predetermined range, automatic tuning is stopped. In the automatic tuning device of the PLL receiver,
After changing the frequency division number of the programmer pull divider, the near-station signal obtained from the intermediate frequency stage or the detection stage
A determining means is provided for determining whether or not the 8th frequency is near the broadcast signal frequency, and only when the determining means determines that the frequency is close to the broadcast signal frequency, the amplifier circuit and the counting circuit are activated, respectively.
An automatic channel selection device characterized in that it operates for a predetermined period of time.