JPS6069861A - Signal processing device - Google Patents

Abstract

PURPOSE:To perform a time base correction processing without using a high- speed memory or the like but with two time slots by performing the time base correction processing, which corrects variance of the time base generated in a transmission system, and a time base compression processing simultaneously with the same memory means. CONSTITUTION:Time base processing circuits 26-29 perform the time base correction processing and the time base compression processing of reproduced data of individual channels of clock reproducing circuits 11-14 and supply reproduced data of a prescribed data rate to a multiplexer (MPX)30. Reproduced data of individual channels of said circuits 26-29 are converted to data of two channels by the MPX30 because the number of channels required simultaneously on the time base is reduced by the time base compression processing, and converted reproduced digital data are subjected to an error correction processing or the like by decoders 36 and 37 and are supplied to a demultiplexer 51. Consequently, a low-speed memory can be used, and the memory capacity is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing device applied to signal C raw silk etc. in a video tape recorder, and particularly to a signal processing device applied to signal C raw silk etc. in a video tape recorder.
The present invention relates to a signal processing device in which a transmission signal subjected to decompression processing is supplied via a signal transmission system.

[11) Technology and its problems] Generally, there is a limit to the transmission speed of information that can be transmitted in a signal transmission system. For example, in a magnetic recording/reproducing system such as a video tape recorder, the recording density of the magnetic recording medium The frequency of signals that can be recorded and reproduced is limited by the transmission characteristics determined by the characteristics of the magnetic head.

Therefore, conventionally, so-called tental video tape recorders that record and reproduce video signals in a decimal state have added redundant hiso1- to the takes in order to correct errors in the transmission takes. In order to reduce the density, the time axis of the Cheetah Ray 1 image take is expanded in the recording system, and then the take is recorded in multiple channels on the recording medium, and time axis compression processing is performed during playback.

Figure 1 shows the operating principle of the above-mentioned technical video table recorder.In the recording system, for example, a hito signal of the NTSC standard television system is converted into a hito signal of an odd field and a hito signal B of an even field. are recorded as digital takes DA and DB of each feed whose time axis has been expanded. Then, in the recycled yarn, the reproduced digital data DA' of each field mentioned above,
The reproduced video signals A and B are formed by time-base compressing the DB and then converting it into analog data.

By the way, in a digital video tape recorder, the data rate of playback data read out from the magnetic tape by a rotating magnetic head during playback operation changes depending on the playback operation mode, and also changes due to speed fluctuations of the magnetic tape and the rotating magnetic head. do.

That is, in a helical skin type video tape recorder that generally uses a rotating magnetic head device, the tracing state of the magnetic tape 1 due to the rotating magnetic head ζ changes depending on the tape running state during playback, as shown in FIG. , the trajectory of the magnetic head in the normal reproduction operation mode (hereinafter referred to as N mode). On the other hand, the trajectory LFS in the variable speed playback mode (hereinafter referred to as F-3 mode) in which the magnetic tape runs at variable speeds in the forward direction becomes longer, and in the variable speed playback mode (hereinafter referred to as R mode) in which the magnetic tape runs at variable speeds in the reverse direction. - The locus LIts in S mode) becomes shorter. Therefore, the frequency of the reproduced data clock also changes depending on the reproduction operation mode, and the frequency becomes higher in the FS mode and lower in the RS mode compared to the frequency in the N mode.

In this way, the data rate 1 of the reproduced data changes depending on the various playback modes, but the image cheek for forming the reproduced video signal, that is, the cheek rate 1 of the reproduced cheek after time axis compression processing is constant. There is a need. Therefore, in the past, data loss and duplication have been avoided by applying so-called time axis correction processing to the reproduced cheeks.

FIG. 3 is a block circuit diagram showing a circuit configuration of a reproduction system of a conventional digital video tape recorder equipped with the functions of time axis correction processing and time axis compression processing as described above.

In the playback system shown in FIG. 3, digital data that has been subjected to time axis expansion processing in the recording system is first obtained by the playback circuit 10 from a recording medium on which multi-channel recording is performed by distributing the digital data to a plurality of channels. Regarding the reproduction signal of each channel, the cheek clock of each channel is reproduced by clock reproduction circuits 11, 12, 13, and 14 using phase-locked loops, respectively. The above reproduction circuit 1
The reproduction signal of each channel obtained by the 01 trowel is processed by each decoder 31, 32 after time axis fluctuations occurring in a signal transmission system using magnetic tape as a recording medium are removed by time axis correction circuits 21, 22 and 23, 24, respectively. 33.34+ will be supplied. The reproduced digital takes of each channel obtained by each of the decoders 31, 32, 33, and 34 are processed using the time axis compression circuits 41, 42, 43, and 44ζ, respectively. The signal is compressed and supplied to the demultiplexer circuit 50.

This multiplexer circuit 50 converts digital data of four channels into, for example, a luminance signal Y, each color difference signal IJ,
Convert to digital data of 3 channels of V. The digital data of the three channels are subjected to error correction processing by error correction circuits 61, 62, 634, respectively, and then sent to each digital/analog D/A converter 7'l, 72.7.
3, and is converted into an analog signal by low-pass filters 81, 82 .
The signal is supplied to the matrix circuit 90 via 83. Above 7
The 1-lix circuit 90 receives an analog luminance signal Y,
Three primary color signals 1 (, , G, 'B' are formed from each color difference signal U, V, and these three primary color signals R', G, B are sent to the monitor device 10.
Supply to 0.

As mentioned above, in conventional signal reproducing systems, it is better to perform various signal processing such as error correction on data rays 1 through which the time axis has been extended, because the processing speed can be kept low and the control required for signal processing can be easily carried out. , the reproduction signal O of each channel obtained by the reproduction circuit 10 is first subjected to time axis correction processing,
Signal processing including error correction etc. is performed on the expanded square data layer 1 by decoders 31, 32, and 3 of each channel.
3.34, and then time axis compression processing.

However, in such conventional systems, time axis correction processing is performed and signal processing including error correction is performed on the expanded Cheetah Ray 1 by the decoders 31 and 32 of each channel.
, 33 and 34, and then time axis compression processing.

However, in such a conventional method, the time axis correction circuit 2
1, 22, 23. Since the magnitude relationship between the input data 1- and the output data 1- at 24 is not uniquely determined,
Even if the memory in the time axis correction processing diagram is controlled by either the input take clock or the output data clock, three time slots are required for the operation of the memory, and each time axis correction circuit 21, 22, 23, 24 Each of them had to be constructed using high-speed memory or parallelized, resulting in an increase in circuit scale.

In addition, each of the Tecoder 31, 32° 33.34 provided on the front stage side of the time axis compression circuit 41, 42, 43. There is a period in which they operate simultaneously on time 11+, which requires a parallel circuit configuration and increases the circuit scale.

Here, in the conventional example shown in FIG. When time axis correction processing is performed in memory, as shown in Figure 4, in order to prevent the write address WA from overtaking the read address and causing data loss, there is a gap between the write address WA and the read address. Appropriate offset I. must be given. When performing time axis correction processing using memory, for example, the reproduced data clock is used as a write clock to write the reproduced tentacle data, and the readout clock of the base thread is used to read the reproduced tentacle data. All you have to do is

In this case, as mentioned above, the frequency of the reproduced cheetah block changes depending on the reproduction mode, and in the special ζI''-8 mode ζ, ■the total number of samples per channel Sp and the variation in the tape running speed a. Since the write address approaches the read address by the product Sp×a, it is necessary to secure an offset of 5 pXa or more between each address.

When time axis correction processing for each channel is performed in memory for each channel, the memory capacity M+ required for each channel is, for example, Sp250000, write clock frequency in N mode 10M171Z, read clock frequency If it is calculated as 13.5MHz, Table 1 shows that the tape running speed in F/S mode and 几/S mode is a=±30 compared to N mode.
% change is 15002 Bytes/cl].

Table 1 also shows that in a memory that cannot perform write and read operations at the same time, the write and read operations are performed asynchronously as described above, so it is difficult to operate using either the write clock or the read clock. Even if managed, it would require three time slots. Therefore, generally, three slots 1- are provided in which data for three samples can be written/read in parallel.

FIG. 5 shows the operating state of the memory that performs time axis correction processing per channel in the conventional example described above. FIG. 5A shows the case of F and S modes, and FIG.
The case of mode is shown.

That is, when performing time axis correction processing managed using the standard read clock, one slot out of every three slots is assigned to the read operation, and in the F-S mode, the remaining one or two slots are allocated to the read operation. By allocating the write frequency m1, the increase in the frequency of the reproduced cheetah block was absorbed.

Furthermore, in the R and S modes, a drop in the frequency of the reproduced take clock is absorbed by allocating a loss slot or one slot to the write operation.

Furthermore, in the time axis compression circuits 41, 42, 43 and 44, fluctuations in the data clock have already been removed by the above-mentioned time axis correction processing, so when performing time axis compression processing in the frames door memory, Data writing/reading may be performed using constant write and read clocks. However, since the number of samples of input data changes according to the variation in tape running speed, the memory capacity M2 required for time axis compression processing is determined by setting the write clock frequency in N mode to jw and the read clock frequency to Letting the number of skins be fR, it is given by J)■.

That is, when performing time axis compression processing in the frame store memory, as shown in FIG.
..., the n)th writing operation end time is tw(k),
Similarly, let the read operation end time be 1n(k), and the read operation start time tOF with respect to the write operation start time 1o.
Assuming that F is given offset 1 hour, the necessary and sufficient condition for writing/reading without causing data loss is T+-jW(+) topv >
0 ・−・・Second formula T2 = tn(n) jw(
n) ') 0 ......Since it is the third equation, from the above second and third equations, toFF<M, Sat 01
81118. , 4th formula % formula %) ......5th formula is obtained, and from the above 4th formula and 5th formula, Sp・(II"
)・(above-above) < topp < M・YuWJRjW ......The sixth formula is obtained, and from this sixth formula, the memory amount M2 required for the above-mentioned first Given.

Here, the memory capacity M2 required for the time axis compression process in the conventional example described above is calculated under the same conditions as the time axis correction process described above, as shown in Table 2, and is 16852 Bytes per channel. Become.

Table 2 [Object of the Invention] Therefore, in view of the above-mentioned conventional problems, the present invention provides a signal processing system that conventionally requires three time slots in a signal processing system equipped with a function of performing time axis correction processing and time axis compression processing. We have developed a signal processing device with a new configuration that makes it possible to perform time axis correction processing in two time slots without requiring high-speed memory or circuit parallelization, and reduces the circuit scale of the entire device. This is what we provide.

[Summary of the invention]

In order to achieve the above-mentioned object, the signal processing device according to the present invention is provided with a signal reproduction system O to which a transmission signal subjected to time axis expansion processing is supplied via a signal transmission system. A time axis correction process for correcting time axis fluctuations occurring in the signal transmission system included in the transmitted signal and a time axis compression process corresponding to the time axis expansion process are performed simultaneously in the same memory means. This is the characteristic of Kokichi.

〔Example〕

An embodiment of the signal processing device according to the present invention will be described in detail below with reference to the drawings.

The full cock circuit diagram in FIG. 7 shows an embodiment of a playback system when the present invention is applied to the above-mentioned conventional decile video tape recorder.

In this embodiment, the reproduction signals of each channel obtained by the reproduction circuit 10 are clock reproduction circuits 11, 12, 13, and 14ζ using phase-locked loops, respectively.
After each take clock is reproduced, it is immediately supplied to the time axis processing circuits 26, 27 and 28, 29 of each channel.

Each of the time axis processing circuits 26.27, 28.29 performs time Ql+ correction processing and time axis compression processing on the reproduced data of each channel whose take clock has been reproduced by the clock reproduction circuits 11, 12, 13.14. and supplies a playback take of a predetermined data rate to the multiplexer 30. Each of the above time axis processing circuits 26, 27, 28, 2
The playback data of each channel that has been subjected to the time axis correction processing and time axis compression processing is divided into two channels by the multiplexer "30" because the number of channels required simultaneously on the time axis is reduced by the time axis compression processing. The two channels of reproduced digital data output from the multiplexer 30 are each subjected to signal processing such as error correction processing by the techoques 36 and 37, and then supplied to the demultiplexer 51. The demultiplexer 51 outputs a luminance signal Y and each color difference signal U from the tental data of the two channels.
.

■Convert to 3-channel tental data.

The digital takes of the three channels are subjected to error correction processing in the error correction circuits 61, 62.63, respectively, and then sent to the respective digital analog D/A converters 71, 72, 73.
Analogized and low-pass filters 81, 82.8
3 to the matrix circuit 90. The above-mentioned multiplex circuit 90 outputs an analog luminance signal Y.
, each color difference signal [J.

Three primary color signals R, , G, and B are formed from (1), and these three primary color signals JG, B are supplied to the monitor device 100.

In the embodiment with the above configuration, if the time axis processing circuit of each channel performs time axis correction processing and time axis compression processing in the same frame storage memory, the read clock is constant and the writing is performed. Since the clock only changes depending on the reproduced data clock, the required memory capacity M3 is given by the seventh equation. When the memory capacity M3 is calculated under the same conditions as in the conventional example described above, it becomes as shown in Table 3 for the fluctuation of the tape running speed a-±
■6852 l3ytc per l channel with 30 chips.

Table 3 also shows that the memory capacity M3 given by the above formula 7 is M3
> 0, that is, fw (1 + a ) < fn, the above-mentioned F-S mode and R-8
In either mode, time axis correction processing can be performed using two time slots. For example, when managing memory operations using a read clock, one time slot is used for write operations as shown in FIG. By allocating O or 1 time slot to the read operation, variable speed playback can be performed without data loss. If the memory operation is performed in two time slots in this way, the time axis processing circuit described above is 15 times slower than the conventional example in which the memory operation is performed in three time slots as described above. 26°27.
Kokichi, which makes up 28.29, is created. Furthermore, on the subsequent stage side of the time axis processing circuit, the number of channels that need to be operated simultaneously is reduced, so the circuit scale can be reduced.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, in the signal processing device according to the present invention, the time axis correction process and the time axis compression process are performed simultaneously in the same memory means, so that the memory operation is performed in two ways. It becomes possible to perform the signal processing in a time slot, and the necessary signal processing can be performed even using a low-speed memory, and the required memory capacity can also be reduced.

Therefore, the intended purpose can be fully achieved.

[Brief explanation of drawings]

FIG. 1 is a time chart 1 showing the principle of signal processing operation in a general digital tape recorder. FIG. 2 is a schematic diagram showing the tracing state of a magnetic head during a reproducing operation in a helical scan type video tape recorder. FIG. 3 is a block circuit diagram showing the circuit configuration of a reproduction system of a conventional digital tape recorder. FIG. 4 is a schematic diagram showing address states of a memory used for time axis correction processing. 5A and 5B are schematic diagrams showing the memory operation of the time axis correction circuit in the conventional example described above. FIG. 5A shows the F and S modes, and FIG. 5B shows the 几 and S modes. It shows. FIG. 6 is a schematic diagram showing the operation of time axis compression processing used in the memory. FIG. 7 is a block circuit diagram showing an implementation flJ of a reproduction system when the present invention is applied to the digital video tape recorder G. FIG. 8 is a schematic diagram showing the memory operation of the time axis processing circuit in this embodiment. 10・・・・・・・・・・・・ Regeneration circuit 11.12
,13.14...Clock reproduction circuit 26.
27, 28, 29... Time axis processing circuit 30...
・・・・・・・・・・・・ Demart flex 0 rec → length 3
5.36... Decoder 51... Matrix circuit patent applicant Sony Corporation representative Patent attorney Kodo Koike Hiroshi Hitoshi -

Claims (1)

[Claims] In a signal reproduction system in which a transmission signal subjected to time 1ζ1j expansion processing is supplied via a signal transmission system, time axis fluctuations occurring in the signal transmission system included in the supplied transmission signal are corrected. A signal processing device characterized in that a time axis correction process and a time axis compression process corresponding to the time axis expansion process described above are performed simultaneously in the same memory means.