JPS6069571A - Test system of logical circuit - Google Patents

Abstract

PURPOSE:To point out an astable element in advance and shorten the time of debugging operation by holding a terminal to be driven in a test at a sense state, one by one, and driving other terminals as well as in the test. CONSTITUTION:Points which are driven in the test are connected to the sensor of an in-circuit tester, one by one, and other points are connected to a driver and driven as well as in the test. Simultaneously, it is checked whether the level of the point connected to the sensor is unchanged or not at a constant level. For example, when an NAND gate 13 is regarded as a test device, the sensor of the in-circuit tester is connected to only a line A and the driver is connected to another line B to drive the points to ''low'', ''high''... according to a truth table during the test. Thus, it is checked whether the level of the line A is constant or not, and whether a flyback occurs or not. This flyback is checked similarly with the line B.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is an in-circuit tester, which is a type of card tester, and has a logic for checking whether spike noise is generated due to the accelerator component of a line leading to a driver or sensor. It concerns circuit testing methods.

[Prior art and problems]

Figure 1 is a diagram showing the configuration of an in-circuit tester, Figure 2 is a diagram explaining an example of testing the logic circuit of a printed board unit, and Figure 3 is a diagram explaining the problem of a circuit under test with a feedback loop. 4 are diagrams for explaining the generation of spike noise. In the figure, 1 is the CPU (
2 is LP (line number printer), 3 is KB (keyboard), 4 is DSP (display),
5 is ps (power source), 6 is driver sensor
Controller, 7 and 7-1 to 7-n are drivers, 8
-1 to f3-n are sensors, 9 is UUT (printed board unit under test)), 10 to 12 are AND gates, 13 and 14 are NAND gates, 15 and 16 are devices, and L is the line accelerator component. In general, a card tester tests the entire printed circuit board unit by applying a test signal to each input terminal of the printed circuit board unit under test and checking the contents of the output terminals, but an in-circuit tester is a test that tests each individual device and confirms the operation of the entire printed circuit board unit under test!・It is intended to carry out the following. In other words, in-circuit testing involves testing a component while it is connected to other components, and generally involves forcing inputs to ICs that are not easily accessible by other means. In this method, the printed circuit board unit under test is tested by putting it into a logic state.

As shown in FIG. 1, the tester has a CPUUI, an LP2. KB3, DSP4, PS5,
It includes a driver/sensor/controller 6, drivers 7-1 to 7-n, sensors 8-1 to 8-n, and the like. The driver/sensor/controller 6 controls the drivers 7-1 to 7-n1 and the sensors 8-1 to 8-n according to instructions from the CPU 1, and controls the UUT 9.
drive or sense a signal at a desired terminal within the circuit. For this purpose, a spring pin is used and this spring pin is erected at the drive or sense point of the UUT9.

In FIG. 2, a circuit consisting of AND gates 10 to 12 and NAND gate 13 shows an example of the logic circuit of UUT 9 shown in FIG. Here, Nando Gate 13
is a test device, pins P1 and P connected to its input signal line are connected to the driver of the in-circuit tester, and pin P3 connected to its output signal is connected to the sensor of the in-circuit tester. During testing, the input terminal of the NAND gate 13 is driven according to the truth table shown in the table.

By the way, as shown in FIG.
such that the output of is returned to the reset input terminal of device 15 via NAND gate 14 and device 16,
If there is a so-called feedback loop,
Tests fail.

For example, consider a case where the NAND gate 14 is tested while a signal is applied to its input terminal so that the output of the device 15 becomes ")". If the reset line cannot be held 1 high, device 15 will be reset and its output will be 10-''.As a result, the output of NAND gate 14, which is being driven by driver 7 of the in-circuit tester, will be reset. When the input level changes, the output level may also change accordingly.In this case, the tester will determine that the test device is defective because the output of the NAND gate 14 will be different from what it expected. However, this problem cannot be solved simply by keeping the reset line at 1 high. This is because the driver 7 of the in-circuit tester is connected to the UUT by a cable of length l, so there is an actance component in this part, as shown isometrically in Figure 4. do. Therefore, the spike fist noise (
flyback voltage) occurs. Normally, the pulse level of a TTL circuit is 0 to 5 ports, but spikes
Noise (flyback voltage) can reach more than ten volts,
This may cause element deterioration or malfunction.

Therefore, to solve the above problem, in FIG. 3, during the period when NAND gate 14 is being tested, the reset line from device 16 to device 15 is
It is necessary to perform an inhibit process on the device 16 so that it does not become 0-". Since this problem is common to all circuits, conventional in-circuit testers do not use an automatic program e-generator. In some cases, the inhibit process described above may be automatically performed.Therefore, several stages of feedback and
If there is a loop, the automatic program will automatically inhibit the loop, but if the logic is deeper, the program will not be able to automatically inhibit the loop. Also, although it is not feedback, in circuits with built-in sequencers, the signal tends to change by changing the clock input.

As mentioned above, it is difficult to create an inhibit procedure in advance in a program for all cases, and as a practical matter, it is not possible to inhibit 100% automatically, and correct operation results cannot be obtained due to spice noise. There are cases. Further, during depacking in an in-circuit tester, many unstable states due to noise occur, but this noise is thought to be mainly caused by incomplete inhibition. Conventionally, for such problems,
The method used is to manually look at the circuit diagram, find the feedback fist loop, and apply inhibition. Therefore, in manual depacking work, it is an important factor to confirm whether inhibition is being performed reliably.

[Purpose of the invention]

The present invention is based on the above considerations, and is a logic circuit that checks whether inhibition is reliably performed in an in-circuit tester, makes it possible to extract unstable elements in advance, and shortens depacking work. The purpose is to provide a test method for

[Structure of the invention]

To this end, the logic circuit testing method of the present invention connects a tester driver/sensor to each input/output terminal of each device that constitutes the logic circuit, and the tester controls the driver/sensor. Drive the signal at the input terminal to change the signal level at the input terminal according to a predetermined test level, and sense the signal at the output terminal of the test device to see if the signal level at the output terminal is at the expected level. In the logic circuit testing method for checking whether the is changed according to the above test level, and the above 1.
The system is characterized in that it is configured to sense the signal of one input terminal and check whether the signal level of the one input terminal has changed with respect to all of the test levels. Further, voltage detection means is provided in parallel with the tester at each input/output terminal to which the driver/sensor of the tester is connected, and the voltage detection means uses a level higher than the level of the pulse of the logic circuit as a reference voltage. The present invention is characterized in that it is configured to transmit a voltage detection signal on the condition that the detected voltage exceeds the reference voltage.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a diagram for explaining one embodiment of the present invention, and FIG. 6 is a diagram for explaining another embodiment of the present invention.

In FIG. 5, A%B and C are A% and C shown in FIG. 2, respectively.
Corresponding to B and C, the end of D is connected to the driver of the in-circuit tester, and the end of S is connected to the in-circuit tester driver.
Connected to the sensor of the tester, H means the drive/sense signal is 1 high, and L means the drive/sense signal is 10-
Therefore, FIG. 5 shows an example in which the present invention is applied to the circuit shown in FIG. 2, and FIG. 5 (α) shows the drive during the test. FIG. 5(h) and (c) show the drive signal according to the present invention.

In the present invention, one of the driving points during the test is
Connect each point to the sensor on the in-circuit desk, and connect the other points to the driver and drive them as you did during the test. During this time, it is checked whether the level at the point connected to the sensor does not change at a constant level. As a result, if the level remains constant, confirm that inhibiting has been performed, and check that the level changes (from 1 high to 10
-" or changes from 'low' to '1 high'), it is recognized that the inhibit is incomplete and flyback will occur.

For example, in the circuit shown in FIG.
3 as a test device, first, as shown in Fig. 5 (
As shown in h), there is no in-circuit connection on the A line only.
Connect the sensor of the tester, connect the driver to the remaining B line, and read 10-", "high", etc. according to the truth table during testing shown in Figure 5 (α). drive. As a result, it is checked whether the level of the A line is constant or not, and whether or not flyback has occurred is checked.

Such a flyback check is similarly performed for line B, as shown in FIG. 5(C).

Furthermore, FIG. 6 shows another embodiment of the present invention. In Fig. 6, 17 is an inverter, 18 is a JK-F
F and D are diode groups, R and r are resistors, and PD is a light emitting element. The series circuit of the diode group and the resistor R is OUT
drive/sense point and ground potential. The diode group is made up of a plurality of diode elements connected in series, and is used to detect spike noise of, for example, more than 7 ports, which causes element deterioration.

Therefore, the connection point between the diode group and the resistor R is UUT
When a spike voltage occurs that exceeds the set voltage of the diode group, 7 volts, it becomes high level. This signal passes through the inverter 17 to the preset terminal P of JK-FF18.
s is supplied. JK-FF18 has preset terminal P
While S is at a high level, that is, no spike noise is detected, it is not preset, and when the Q terminal is at a high level and spike noise is detected, it is preset and the Q terminal changes from high level to low level. change.

As a result, a current flows through the light emitting element PD and an optical signal is sent out. Then, when the reset signal *RESET applied to the clear terminal CLR is set to high level (R1 and SET are low level), JK-FF18 is reset and Q
The pin becomes high level again.

As described above, the present invention shown in FIG. 6 is used to investigate the occurrence of spike noise due to the line and accelerator components leading to the driver and sensor of the Inserkit tester. A spike noise detection means is connected in parallel to the pin P or P3 of the circuit using an IC clip or the like to detect spike noise, and the spike noise is latched into a flip Φ-flop.

Therefore, by preparing a plurality of such circuits, for example, about 14 or 18, and setting them in an IC clip, it is possible to detect spike noises that cause element deterioration with simple operations. can. Furthermore, it is possible to notify the in-circuit tester of the timing at which spike noise occurs by using the output of the flip-flop as a trigger signal. As mentioned above, since noise is thought to be mainly caused by incomplete inhibition, it is possible to check whether inhibition is being performed reliably by the presence or absence of noise.

In addition, if the present invention detects spike noise in which the level of the driving/sensing point of the UUT exceeds the reference level which is higher than the pulse level (5 volts) of the logic circuit, the configuration is particularly suitable for the sixth point. It goes without saying that the circuit is not limited to the one shown in the figure, and that various modifications can be made.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, inhibiting is reliably executed by setting one terminal of the terminals to be driven during testing to a sense state and driving the other terminals in the same manner as during testing. Since it is checked whether or not the above conditions are met, unstable elements can be extracted in advance by adding a simple program, and the depacking process can be shortened. In addition, with a simple circuit configuration using diodes and flip-flops, it is possible to check for the presence of spike noise that causes element deterioration, making it possible to identify unstable elements in advance in an in-circuit tester and prevent element deterioration. It is possible to prevent this and shorten depacking work.

[Brief explanation of drawings]

Figure 1 shows the configuration of the in-circuit tester, Figure 2 shows the configuration of the in-circuit tester.
The figure shows an example of testing the logic circuit of a printed circuit board unit. Figure 3 explains the problem of a circuit under test with a foot loop. Figure 4 explains the occurrence of spike noise. , FIG. 5 is a diagram for explaining one embodiment of the present invention, and FIG. 6 is a diagram for explaining another embodiment of the present invention. 1...CPU (Central Processing Unit), 2...LP (line printer), 3...KB (keyboard), 4.
...DSP (display), 5...PS (power Φ
source), 6...driver/sensor controller,
7 and 7-1 to 7-rule...driver, 8-1 to f3-n...sensor, 9...UUT (printed board unit under test)), 10 to 12...and number gate, 13 and 14... Nando Gate, 15 and 16...
...Device, L...Line glue accelerator component, 17
...Inverter, 18...JK-FF%D...Diode group, R and r...Resistor, PD...Light emitting element.

Claims (2)

[Claims] (1) A tester driver/sensor is connected to each input/output terminal of each device that makes up the logic circuit, and the tester controls the driver/sensor to drive the signal at the input terminal of the test device and Logic that changes the signal level of the input terminal according to a predetermined test level, senses the signal of the output terminal of the test denomination chair, and checks whether the signal level of the output terminal is at the expected level. In the circuit law method, the tester drives the signals of the remaining input terminals of the test device except for one, and changes the signal level of the remaining input terminals according to the test level. and is configured to sense the signal of the one input terminal and check whether the signal level of the one input terminal has changed with respect to all of the test levels. A test method for logic circuits. (2) Connect a desk driver/sensor to each input/output terminal of each device that makes up the logic circuit, and the tester controls the driver/sensor to drive the signal at the input terminal of the test device and Logic circuit testing that changes the signal level of the input terminal according to a predetermined test level, senses the signal of the output terminal of the test device, and checks whether the signal level of the output terminal is at the expected level. In this method, voltage detection means is provided in parallel with the tester at each input/output terminal to which the driver/sensor of the tester is connected, and the voltage detection means is configured to:
A logic circuit characterized in that the reference voltage is set at a level higher than the pulse level of the logic circuit, and the voltage detection signal is sent out on the condition that the detection voltage exceeds the reference voltage. Test method.