JPS6068722A - Electronic device - Google Patents

Abstract

PURPOSE:To omit a customized work required due to a blown fuse by specifying the relation of connection between logical elements at the inside of a semiconductor device by means of connecting information stored in a built-in storage element so as to cope with the logical change. CONSTITUTION:FF9a, 9b are storage elements specifying the relation of connection, and since an output of an OR circuit 8a gives the same logical value as that of an output of a buffer 1a when an output of the FF9a is zero, it is equivalent that the buffer 1a and an AND circuit 2a are connected. Since an output of an OR circuit 8b is logical 1 at all times independently of the output value of a buffer 1b when the FF9b is logical 1, the AND circuit 2a acts like a simple buffer. When the FF9b outputs logical 1, it is regarded that the buffer 1b and the AND circuit 2a are not connected.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electronic device using a semiconductor device whose internal logic circuits can be freely recombined as necessary to realize an arbitrary logic function. It is related to.

[Prior art]

Semiconductor technology has made remarkable progress in recent years, and large-scale integrated circuits
SI has come to be widely used, but LS, which can be freely designed as needed, is similar to so-called random logic.
Circuits unsuitable for integration remain in small-scale standard logic devices, namely 881. This has been realized by combining a large number of Mals, which has been an obstacle to improving the packaging density.

Conventionally, this LSI and 881. Fuse-type logic elements such as FROM (programmable read-only memory) and PLA (programmable logic array) have been used to fill the gap with MSI.

The principle of PLA will be explained with reference to FIGS. 1 and 2. In FIG. 1, 1a.

1b is a buffer 7.2 AND gate, 3a and 3b diodes, 4a fuse, and 4b is a blown fuse. The output of the buffer 1a connected to the diode 6a and the unblown fuse 4a and the AN
The inputs of the D gate 2 are connected to each other.

On the other hand, the output of the buffer 1b, which is connected to the diode 3b through the blown fuse 4b, and the input of the AND gate 20 are not connected to each other.

In Figure 2, 2a and 2b are AND gates, 5-digit CI
Iya Gut, 6a, 6b are transistors, 7a &i
Mitsuuse 7b is a fuse that has been fused. Vc
c is the power supply voltage. The transistor 6a and the fuse t
ANI connected by fuse 7a)
The output of the gate 2a and the input of the OR gate 5 are connected to each other. On the other hand, the output of the AND gate 2b and the input of the OR gate 50, which are connected to the transistor 6b by the blown fuse 7b, are not connected to each other.

1) LA has a large number of ANDs inside the semiconductor device in advance.
Arrange logic elements such as gates and OI't gates,
These input/output signals are connected to each other using fuse logic as shown in FIG. 1 or 2. Immediately after manufacturing, the fuses at all connection points of the PLA are in an unblown state. PLA users are! Through a unique external interface, specific internal fuses are fused to realize the desired logic function (this process is called customization work). To achieve different logics, fuse different fuses.

According to the above [7], conventional fuse-type logic devices are AND
Since the connection relationships between logic elements such as game-OR gates are defined by the presence or absence of fuses, customization work is first required to realize a desired logic circuit using fuse-type logic elements. For this purpose, a dedicated writing device is required to blow out the fuse inside the logic device.
The user of the fuse-type logic device must either purchase this writing device or request customization from the manufacturer of the fuse-type logic device, but in either case, the disadvantage is that it requires extra cost and time. However, once customized, the logic cannot be changed.

[Summary]

This invention was made in order to eliminate the drawbacks of the conventional devices described above, and instead of defining the connection relationships between internal logic elements by the presence or absence of fuses, it is defined by the storage contents of built-in storage elements. An object of the present invention is to provide an electronic device equipped with a means for inputting connection information into a memory element of the semiconductor device.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with respect to m 7 [+ from FIG. 6. In the figures, the same reference numerals as in FIG. 1 or 2 indicate the same or corresponding parts. In FIG. 3 (4), 8. a, 8b OR gate, 9a.

Reference numeral 9b is a flip-flop that stores connection relationships.

However, the output of this 7 lip-flop 9a is logic "a"
At this time, a connection relationship is established between the output of the buffer 1a and the input of the AND game a. In such a case, the connection point consisting of the OR gate 8a and the 7-lip flop 9a is made by intersecting the output line of the buffer 1a and the input line of the AND gate a, as shown in FIG. I will represent it with a circle.

On the other hand, the output of the flip-70 tube 9b is logic "1", and at this time there is no connection between the output of the buffer 1b and the input of the AND gate 2a. In such a case,
The connection point composed of the OR gate 8b and the seven lip-flops 9b will be shown without a mark, such as the intersection 10b in FIG. 3 (+3).

Similarly, in FIG. 4(A), 12a and 12b are A N l) gates, and 13a and 13b are clip-flops that store connection relationships. However, flip-7
The output of the 0 knob 13a is logic "1", and at this time the AN
A connection relationship is established between the output of D game a and the input of OR gate 1130. In such a case, AND gate 1
2a and the flip-flops 13alC and C are represented by square marks, such as the intersection 14a in FIG. 4CB). .

On the other hand, the output of the flip-flop 13b is a logic “
In this case, the output of the AND gate 2b and the input of the OR gate 11a are not connected.
The connection point constructed in 3b is the intersection 1 in Fig. 4 (13).
It will be expressed without a mark like 4b.

Next, FIG. 5 shows an example of a semiconductor device that can realize an arbitrary logic circuit using the circuits shown in FIGS. 3 and 4. In Figure 5, only the slip-flops that memorize the connection relationships at each intersection are extracted, and a single shift register 1 is created.
5 is a summary. The output of each bit of this shift register 15 is connected to the intersection point corresponding to the number, and constitutes the circuit shown in FIG. 6 (5) or FIG. 4 (4), respectively.

For this shift register 15, a shift input terminal 16
When inputting a bit pattern as shown in FIG. 5 using the shift clock terminal 17, the bit patterns 10a to 10h
At each intersection indicated by , a connection relationship occurs only at the intersection corresponding to the bit outputting logic "O", and symbols 14a to 14h
At each intersection indicated by , a connection relationship occurs only at the intersection corresponding to the bit outputting logic ``1''. Therefore, in the case of the bit pattern in Figure 5, it is equivalent to the logic circuit in Figure 6. .Bit input to the shift register 15 above
By changing the pattern, other logic circuits can be realized. By increasing the types and number of logic elements built into a semiconductor device, more complex logic circuits can be realized.

Next, an electronic device using the semiconductor device described in FIG. 5 above will be described. Reference numeral 19 is the above-described semiconductor device whose internal logic can be recombined from the outside, and 20 is an RO that stores internal connection information to be written in this semiconductor device.
M (IJ-do-only memory), 21 is this RoM2
A write circuit 22 which generates a shift input cutter and a shift clock which are actually read into the semiconductor device 19 from the internal connection information stored in 0 is a micro write processor that controls these as a whole. The semiconductor device 19 is used as a part of another logic circuit 26 of this electronic device, and is therefore connected to other logic circuits through logic inputs 11 to In and logic outputs 01% On.

Next, the operation of this electronic device will be explained.

First, when the electronic device is powered on and starts its initial operation, the microprocessor 22 reads connection information from the ROM 20 and writes it to the write circuit 21 before other logic circuits 23 start operating. send to The write circuit 21 performs appropriate processing, such as parallel-to-serial conversion, on the sent connection information, generates a shift clock, and writes the connection information into the semiconductor device 19. After the write operation is completed,
The microprocessor 22 and other logic circuits 26 start operating, and the semiconductor device 19 also starts operating as a part thereof. In this way, the entire Yukichiko device also starts operating in accordance with its original purpose.

Incidentally, in the above embodiment, a single semiconductor device 19 was used, but a large number of semiconductor devices can be used as necessary. Further, there is no need to provide a dedicated device for convolving internal connection information in the microprocessor 22 and the semiconductor device 19.
For example, a microprocessor provided to control the intended operation of the entire electronic device may be used to write internal connection information of the semiconductor device 19 only during initial operation. Similarly, the ROM 20 does not need to be dedicated to storing internal connection information, and other micro programs and the like can be stored at the same time.

Further, an external storage device such as a magnetic disk may be used instead of the ROM 20 for storing internal connection information of the semiconductor device 19. In this case, all connection information is read from the external storage device during initial operation, and may be written into the semiconductor device 19.

〔Effect of the invention〕

As described above, the present invention provides a semiconductor device including a plurality of logic elements such as AND gates and OR gates, and a memory element such as a slip flop or shift register that defines the connection relationship between these logic elements; A storage device such as a ROM that stores connection information of the semiconductor device, a one-input circuit that reads connection information from this storage device, and writes the connection information to the storage element built in the semiconductor device, a microprocessor, etc. It is equipped with a processing device, and the connection relationships between logic elements inside the semiconductor device are defined by the connection information stored in the built-in memory element, instead of the conventional method of using or not using fuses. Moreover, the connection information is automatically written from the storage device to the semiconductor device during the initial operation of the electronic device in which this semiconductor device is used, so there is no need for the customization work of blowing out fuses as in the past. becomes.

For electronic equipment that already has a built-in microprocessor or ROM for other purposes, only a small amount of new electronic circuitry is required, and connection information can be recorded at the same time as the microprogram, so the process It is possible to realize the required electronic device at low cost and in a short period of time without causing an increase in the number of devices.

Even if a change occurs in the logic, it can be dealt with simply by changing the connection information.

[Brief explanation of drawings]

1 and 2 are block wiring diagrams of a conventional 7-use type logic element, FIGS. 6 and 7 show an embodiment of the present invention, and FIGS. 6 and 5 show a semiconductor device. 6 is an equivalent circuit diagram of FIG. 5, and FIG. 7 is a block diagram of the electronic device. 2. 2a, 2b, 2c, 2d: AND gate, 11. 11a, 11b: OR gate, 13a. 16b; 7-lip Φflop; 15: shift register; 19: semiconductor device; 2o: aoM; 21: writing circuit; 22: microphone cffΦ processor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 3 Figure 14 (A) (B) Clam 5 [! J Procedural Amendment (Voluntary) 1980 "JJ2211, Name of invention Electronic device 3, Ministry of affairs r1 to be amended - Which relationship ↑ Near patent applicant address 2-1 Marunouchi, Chiyoda-ku, Tokyo" 2-3 Name (601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama Part 4, "Detailed Description of the Invention" and 1 Brief Description J of Drawings in the agent's specification. 6. Contents of the amendment (1) On page 4, line 16 of the specification, 1-[Summary of the invention]” should be amended to 1 [Summary of the invention]. +21FvjmiFF8 page 6 h (D l %7 No. 1
9Li: J'er m 7 In the figure, the code 19 is corrected as ". (3) I'13a, 13bj on page 12, line 3 of the specification
[9a. 9b, 13a, ], 3bJ. that's all

Claims (1)

[Claims] A semiconductor device including a plurality of logic elements and a memory element that defines connection relationships between the logic elements, a memory device that stores connection information of the semiconductor device, and a memory device that reads the connection information from the memory device, An electronic device comprising: a processing device for writing connection information into the above-mentioned memory element built into the electronic device.