JPS6063688A - Graphic processor - Google Patents

Abstract

PURPOSE:To easily extract features from graphic information for the various directional components of a graph. CONSTITUTION:For example, when data 0-10 are written in a memory 10, read data 0-7 from the memory 10 are written in the addresses 0-7 of a memory 20 by the 1st scanning of Y=0 and X=0-7. The sums 0, 2, 4, ...14 added with the read data 0-7 from the memory 10 and the read data 0-7 from the memory 20 are written in the addresses 0-7 of the memory by the 2nd scanning of Y=1 and X=0-7. The sums 3, 6, ...21, 8 added with read data 1-8 of the memory 10 and read data 2, 4, ...14, 0 of the memory 20 are written in the addresses 1-8 of the memory 20 by the 3rd scanning of Y=2 and X=0-7.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a graphic processing device that performs feature extraction and recognition of graphics, and is intended to speed up feature extraction.

Prior Art and Problems A graphics processing device that performs feature extraction and recognition of graphics includes a large-capacity storage device that stores input graphics, and a small storage device that reads out and stores portions of the graphics within a rectangular area to be recognized from this storage device. It is usually composed of a large-capacity buffer memory and a graphic processing section that reads graphic information from the buffer memory and performs feature extraction, recognition, etc. Typically, the buffer memory consists of an X, Y address generator and a readable and writable RAM (Random Access Memory) for two-dimensional access. The graphics stored in the buffer memory are read out bit by bit and processed by the graphics processing section.

The feature extraction circuit of the graphic processing section counts various feature amounts, and the recognition circuit recognizes the graphic based on the results. - To explain the case of recognizing one side of a triangle as an example, assume that a triangle is written as shown in FIG. 1 in the buffer memory that stores the graphic part within the rectangular area to be recognized. The memory cells with diagonal lines here store data “1” (black), and the remaining memory cells without diagonal lines store data “0”.
Assume that ゛ (white) is memorized and ``1'' (black) represents the side of a triangle. One side of the triangle is a line at 45° to the It is sufficient to check whether the number exceeds a certain darkness value, and the number of consecutive black dots in the 45" direction on the X axis becomes the feature quantity.

However, while it is generally easy to access memory in the horizontal or vertical direction, it is not easy to access the memory in the diagonal direction. That is, X for address generation.

If a Y counter is provided, the X counter will be incremented by 1 in sequence,
After accessing one line (memory cell in the X direction), increase the Y counter + ILX count by 1 again from the beginning.
Then, if you repeat Kaheru 1 mulberry production, you can access the horizontal direction (
TV scan type access), X on the counter,
If you switch Y and perform the same operation, you can access vertically (90
° rotated TV scan type access), but
Diagonal access is not easy because it requires the X and Y counters to be increased or decreased by a predetermined amount at the same time. Therefore, in the conventional method, since it is difficult to access the memory in the direction of 45 degrees to the X axis, another special Wi amount is used instead of the feature amount. However, for triangles and the like, it is quite natural to select diagonal line segments as the feature.

OBJECTS OF THE INVENTION An object of the present invention is to provide a graphic processing device that can easily extract features for various directional components of a graphic based on graphic information.

1. Structure of the Invention The graphic processing apparatus of the present invention records graphic information according to two-dimensional addresses of horizontal and vertical addresses. a
a horizontal address generator, a vertical address generator, a function generator whose inputs are the horizontal address, the vertical address and a constant; addressed by the output of the function generator; a readable and writable second storage means for storing feature amounts in each entry, data read from the first storage means and a second
The present invention is characterized in that it is constituted by a feature extraction calculation circuit that performs a feature extraction calculation using the feature quantity read out from the storage means and writes the result into the second storage means. explain.

Embodiment of the Invention FIG. 2 shows an embodiment of the invention, in which reference numeral 10 denotes a memory (equivalent to the buffer memory described above) in which graphic data is written and read out. WDI & other write data, RDI is read data.

Addresses for accessing memory 10 are generated by an X address generator 12 and a Y address generator 14. The X7 address is the bit or column address of the memory, and the Y address is the word or row address. X, X address generator 12.14 is a counter, memo IJ 10
As shown in FIG. 1, if G is for an 8×8 memory cell, the
2 overflow pulses are counted, and θ~7 are similarly counted. As a result, the memory 10 is accessed in a television scan type, and when the Y address generator 14 reaches the maximum value, 7 in this example, and in this state, the X address generator 12 reaches the maximum value, 7 in this example, one front scan is performed. ends. Therefore, writing only needs to stop when both the X and Y address generators reach their maximum values, and the same goes for reading. Reference numeral 16 denotes a function generator which inputs an X address, a Y address, and a constant K, and generates a function value by varying these and using the constant.

The value of this function becomes the address of the second memory 20, and is therefore rounded off in this example.

The first memo January 0 is a two-dimensional memory, but the second memory 2
0 is one-dimensional memory. FIG. 3 shows these memories, and the memory contents of the two-dimensional memo I710 are 0.1.2.・・・
...It is shown in 9.10.

In FIG. 2, reference numeral 22 denotes a feature extraction arithmetic circuit which also has a read/write function for the memory 20, and writes the data RDI read from the memory 10 to the address output by the function generator 16 of the memory 20. The data RD2 written at the address of memory 20 is read out, a predetermined feature extraction operation is performed on the read data RD1 using the data RD2, and the result W D 2 is written to the address of the memory 20. In this example, the feature extraction operation is addition, that is, RD1+R.
It is D2.

To explain the operation, the function generator 16 generates (2X+Y)/2
Suppose that occurs. This is the case when 2=2 and it is used as the coefficient of X. X, Y change as mentioned above, 1
In the second scan, y=o.

Since X-0 to 7, the output of the function generator 16 is O to 7.
In the second scan, Y=1. Since X=O~7, the output of the function generator 16 is still 0~7 (rounded down), and in the third scan, Y=2. Since X=0 to 7, the output of the function generator 16 is 1 to 8, and the following applies, and in the last scan, Y=7. Since X=O~7, the output of the function generator 16 is 3~10. Therefore, in this example, the memory 20 only needs to have addresses from 0 to 10. Assuming that data O to 10 are written in the memory 10 as shown, the first scan y=o, x-I=
At addresses O-7 of the memory 20, data 0-7 read from the memory]O are written to addresses O-7 of the memory 20. Second scan Y=1. For X=O~7, addresses 0~7 of memory 20
The sum of the read data O to 7 of the memory 10 and the read data 0 to 7 of the memory 20 is 0, 2.4 . ...14 is written.

Third scan Y=2. When X=0 to 7, the read data 1 to 8 of the memory 10 and the read data 2, 4 .・・・・・・Sum of 14.0 3,6. ...21,8 is written. The same applies below.

As a result of such processing, the memory 20 address 0°1.2
．． The sum of the stored data of the memory cells connected by the wavy lines is written into the memory 10, and the memory 10 is scanned diagonally (60 degrees on the X axis), and the a data written on the scanning line is written. This means that we have achieved a peace of mind. Therefore, if there is an image line on this scanning line, the data stored in the memory 20 for that pulse is large. For example, if there is a piece of cotton on the line 11, the data stored at address 7 of the memory 20 is large, and the memory 2
It is effective for figure recognition and processing.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a buffer memory, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram explaining a memory scan mode. In the drawing, 10 is a first storage means, 12 is a horizontal address generator, 14 is a vertical address generator, 16 is a function generator, 20 is a second storage means, and 22 is a feature extraction calculation circuit. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi 1 Figure 01234567 Figures 2 and 3

Claims (1)

[Claims] A first readable/writable storage means for storing graphic information according to two-dimensional addresses of a horizontal address and a vertical address; a horizontal address generator; a vertical address generator; a function generator that performs a function generator, a readable and writable second storage means that is addressed by the output of the function generator and stores a feature amount in each entry, data read from the first storage means and a second storage means. Special @ read from
A graphic processing device comprising a feature extraction calculation circuit that performs a feature extraction calculation based on a quantity and writes the result into a second storage means.