JPS6062136A - Arranging method of cell on design of lsi - Google Patents

Abstract

PURPOSE:To obtain the arrangement of cells, through which convergence is accelerated to a large-scale information, by repeating and improving operation at the collective unit of the cells, preventing so-much dependence on an initial arrangement of a final cell arrangement and considering a classification in the improvement of arrangement at the collective unit of the cells. CONSTITUTION:Pairs of cells with few terminals, which must be connected at the same potential, in cells 21...2n are formed, and allotted to m lines B. The pairs are divided so that an interline connection is minimized at that time. Lines Bj and Bj+1 are united temporarily to form a line Bj,j+1, a redivision is executed while other lines are left as they are, and the total number of signal lines S not connected to any cell while penetrating the lines B is minimized. An improvement in the unit fundamental operation is repeated thoroughly, Y coordinates are obtained from the best arrangement, and operation is improved partially so as to reduce total signal line length by the exchange of adjacent cells and the inversion of the cells on the basis of the kinds of the arrangement of the selected cells in each line and X coordinates are acquired. When a division into classes of the cells is classified and an optimization is slowly progressed partially after an arrangement under the whole situation, the efficiency of processing can be enhanced. According to the constitution, the arrangement and design of a complicate LSI can also be automated.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method of arranging cells in LSI design, and particularly to polycell type LSI design.

<Prior art> Polycell type LSI is one of the LSI design automation methods
There is a design.

In the polycell system, Sl is a layout cell designed in advance for each logical function unit (for example, a logic gate or 7 circuits) and registered in a library, and a gate 'k' of a given logic circuit diagram. ) tD An LSI that realizes a given logic circuit by allocating cells, arranging these cells in 7-lays, and interconnecting them.

The characteristics of this method are that the height of the cell is kept almost constant, but the width can vary depending on the logical function to be realized, and since the absolute position of the cell is possible, the channel width can be changed according to the wiring requirements. The point is that it is possible.

The problem with cell placement in polycell type LSIs is to completely determine the relative positions of cells on the chip in order to minimize the chip area after wiring. However, in actual design, the entire chip area cannot be accurately known unless wiring is performed after cell placement, so an objective function is required to evaluate the quality of placement without wiring. It is actually difficult to determine the optimal placement, and in conventional cell placement methods, the overall placement design is divided into an initial placement and its iterative improvement. It is common to perform iterative improvements by moving cells, exchanging l for l, chaining cell moves, etc. However, in such cell placement methods, placement improvements are not applied to cell sets with many interconnection requirements, and tend to result in local placement improvements. In addition, the placement after iterative improvement strongly depends on the quality of the initial placement, and even if improvements are made, the purpose will not be fully achieved, and the design of tSl will be difficult to obtain a good initial placement. There was an inconvenience that

<Objective of the Invention> The present invention is capable of iterative improvement in units of cell sets, by making the final cell arrangement less dependent on the initial arrangement, and by hierarchizing the arrangement improvement in units of cell sets. We provide a cell placement method that converges quickly even for large-scale data.

<Example> The cell arrangement method according to the present invention hierarchically executes the arrangement improvement method called Shirt 1 Lug (described later). , until the number of sets that match the number of rows is reached.Thus, we first obtain a general cell arrangement and then gradually work out a more detailed arrangement, which prevents us from settling on a local solution. can.

In order to execute all the placement methods as described above, as shown in Fig. 1, the objective function is a virtual cut line for a chip If in which a large number of cells 21, 22, . . . 2n are arranged in an array of multiple rows. J! 1. ．． l! 2.lk, the arrangement is improved through all iterations so as to minimize the number of signal lines that cross this cut line. In the figure, the horizontal region between adjacent rows is a channel, which, together with the vertical region between cells, is used as a wiring region.

The arrangement method according to this embodiment consists of two processes.

Process 1'''C allocates cells to rows and determines the Y coordinate of the cell position, and Process 2 arranges each cell within the row and determines the X coordinate of the cell position. This is a process for improving placement.

In the initial arrangement of process 1, assuming that the number of rows is m, first find fm cells with few mutually shared nets (terminals to be connected to the same potential), set them as ffi seeds, and form a set of m cells (hereinafter referred to as a group). ) and assigns it to a row. At this time, the division is performed so that the net common f number between each row is minimized. Next, in order to improve the arrangement in process 1, these cells are redistributed into rows fj'k by a shuffling method to be described later. Process 2 uses the same method as Process 1, but stores the position determined in Process 1 in the cell row.

The shuffling method will be explained below using FIGS. 2(a), (b), and (c).

The set of cells allocated to the first row is Bi, and the total number of signal lines SI+S2, .

〔basic operation〕

Cells 21, 22..., 21 as shown in FIG. 2(a)
For a set of cells Bi, Bi+l containing 1,212, etc., temporarily set the set of cells Bi, Bi+l as one set Bi.

Merge into i+1. (FIG. 2(b)] f2) Bi + Bi Keep m of cells other than i+l unchanged and Bi such that TeHk after re-division is minimized.

k°engine B i+l to B11. Re-divide into Bi′l−■ and create a new Bi←B 'i + B i+l ←B 1'+1
shall be. (Figure 2 (C)) The unit operation of shuffling is the above basic operation "t i ', 1 l to (m-t
), then (m-2) 1-. This refers to what is done in step 4.

The arrangement is improved by shuffling until there is no further improvement, and the best arrangement is obtained and the Y coordinate is determined.

Cell placement within each row is executed for the set of cells allocated to each row by the placement improvement described above, and the X coordinate is determined. That is, in each row, seed selection is performed, and based on the selected seed, local improvement is performed such that the line signal line length is reduced by exchanging adjacent cells and inverting cells, and the X coordinate is determined. .

It is possible to improve the performance of the processing by hierarchizing the processing for the cell grouping described above, giving priority to the global arrangement, and gradually optimizing the local arrangement. An overview of layering is given below. Let +gi be the number of sets in the first layer.

(2) Iteratively improve the cell set in the g11 set using the above shuffling method.

(2) Generate g1+1 groups from the lucky g1 groups, where gi is the number of groupings in a certain hierarchy.

As shown in FIG. 3, the set of g1 cells is subdivided into g i -11 silks, with the total sum of cells IJ being approximately equal.

■ gi + I [Shuffling Kanaishi for the solid group now.

The above operations are performed for an appropriate number of layers (1).

For example, gi = 5, g2 = I O, g3 = m
='20, initially 5 sets are generated, and the remaining 9 sets are generated by shuffling, as shown in the fully improved selection procedure, 10 sets are generated from 5 sets, and the groups are divided. Improve iteratively. Then, 20 sets are generated from 10 sets, and as a result of iterative improvement, m=20 sets are achieved.

Effect> According to the present invention, in the cell arrangement of LSI design,
Excellent results can be obtained without the final placement being too dependent on the initial placement, and the processing operations also depend on layered placement improvements for each cell set, so data processing is extremely quick. is performed, has a fast execution speed,
Design can be automated even for complex LSIs.

[Brief explanation of drawings]

Claims (1)

[Claims] 1) In an LSI in which a plurality of cells including at least one logical functional unit are arranged in a chip, an initial arrangement is given to each cell to generate a cell set, and the cell Generate a merged cell set by merging desired sets of sets! -1 LSI characterized in that the merged cell set and the remaining cell set are subdivided into highly optimized placements and a placement is given to each cell.
Cell arrangement method for setup a1. 2] The 111 division for optimizing the cell arrangement is as follows:
2. The cell placement method for LSI design according to claim 1, wherein hierarchical processing is performed by gradually advancing optimization from global placement to local placement. 3) The LSI according to claim 1, wherein the optimization of the cell set is achieved by minimizing the number of signal lines that cross lines set in advance in the cells.
How to place cells in your design.