JPS605344A - Abnormality detector - Google Patents

Abstract

PURPOSE:To speed up the recovery to normal operation by detecting edges of an output signal of a specific period to be processed in time series, and resetting a processor when the level of the signal generated by integrating the edges is larger than a set value. CONSTITUTION:The output signal of a microcomputer 1 is supplied to an edge detecting circuit 4 to detect edges. Its edge detection output is integrated by an integrating circuit 8 to detect whether the integral output is within a specific level range set by a 2-level detecting circuit 10 or not. When the output is not within the specific level range, a flip-flop 13 is triggered and the microcomputer 1 is reset through a resetting circuit 3. Consequently, the recovery from abnormal operation to normal operation is performed speedily.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality detection device for a processing device that processes according to a preprogrammed procedure.

BACKGROUND ART In recent years, high-precision engine control has become required in order to control exhaust gas and improve fuel efficiency in automobiles, and microcomputers with high processing capabilities have come to be used. The microcomputer is a stored program type and has the ability to process in time series according to a preprogrammed procedure, and its processing ability can be improved as the program storage capacity increases. Therefore, since the functionality can be improved without increasing the circuit scale, the field of application thereof tends to expand more and more. However, because microcomputers operate in a chronologically serial manner, once they are taken out of normal sequential operation for some reason, they are often unable to return to normal operation. For this reason, as shown in FIG. 1, a system has been adopted in which the operation of the microcomputer is monitored and when an abnormality occurs, the microcomputer is reset and restarted.

FIG. 1 is a block diagram showing a conventional abnormality detection device.

Note that input parts other than the abnormality detection part are not shown in the figure. In the same figure, (1) is the output terminal (1a) to which the oscillation signal shown in Fig. 2 (a) is output, which is reversed every time To according to the program in a normal state, and the output terminal (1a) in Fig. 2 (a) in an abnormal state. c.
) Reset terminal (1b) into which the reset signal shown in
(2) is a triggerable monostable multi-pipe rake circuit, and when in operation, the microcomputer processes input signals and outputs predetermined output signals according to a predetermined program. (3) is an oscillation circuit, which outputs a pulse with a pulse width Ts (Ts>To) shown in FIG. 2(c).
This is a reset circuit that outputs the reset signal shown in FIG.

Next, we will discuss the operation of the abnormality detection device with the above configuration in the second section.
This will be explained with reference to FIG. 2(a) to FIG. 2(c). First, between time to and time t1 when the microcomputer (1) is operating normally, the output terminal (1a) of the microcomputer (1) is An oscillation signal that is inverted is output.

Therefore, the output signal of the abnormality detection circuit (2) is at the "H" level as shown in FIG. 2 (G). Therefore, the reset circuit (3) does not output any output signal as shown in FIG. 2(e). Next, at time tl, if an abnormality suddenly occurs in the sequential operation of the microcomputers (1) and (7) for some reason, the oscillation output from the output terminal (1a) of the microcomputer (1) The signal stops as shown in FIG. 2(a). Therefore, as shown in FIG. 2(b), the abnormality detection circuit (2)
After s, an output signal at the rLJ level is supplied to the reset circuit (3).

Therefore, the reset circuit (3) is operated by this "L" level input signal and generates the output signal shown in FIG. 2(c). The pulse width TRI of this output signal is set to the time required to reset the microcomputer (1), and the time width TR2 is set to be longer than the time To. In this way, the microcomputer (1) is reset by the reset circuit (3), and the above-mentioned oscillation signal waveform is obtained at the output terminal (1a) during the time To, and the operation of the reset circuit (3) is The microcomputer (1) then returns to normal operation.

However, conventional abnormality detection devices can detect an abnormality when the oscillation signal output from the output terminal (1a) of the microcomputer (1) stops during an abnormality, but when the microcomputer (1) Since the series force processing is performed sequentially, if an oscillation signal with a period shorter than the time To is output as an abnormal state, it is judged as normal, and there is a drawback that the abnormal state cannot be detected. Ta.

Therefore, an object of the present invention is to accurately and quickly detect abnormalities in any processing device such as a microcomputer;
An object of the present invention is to provide an abnormality detection device that can quickly return to normal operation.

In order to achieve such an object, the invention performs arithmetic processing in time series according to a preprogrammed procedure, detects edges of an output signal of a predetermined period generated from a processing device according to the program, An edge detection circuit that generates a pulse signal with a predetermined pulse width for each edge, an integration circuit that integrates the output of this edge detection circuit, and whether or not the output voltage of this integration circuit is within a predetermined set voltage range. A two-level detection circuit that discriminates between
and a reset circuit that receives the output of the level detection circuit and repeatedly supplies a reset signal at regular intervals to the processing device when the output of the integration circuit is outside a predetermined set voltage range. This will be explained in detail using an example.

FIG. 3 is a circuit diagram showing an embodiment of the abnormality detection device according to the present invention. In the same figure, (4) is the resistance (5a)
, the capacitor (6a) and the exclusive OR circuit (7) which outputs the signal shown in FIG.
An edge detection circuit that is triggered by both the leading and trailing edges of the oscillation signal shown in FIG. 4 and outputs the pulse signal shown in FIG. ) and transistors (9), (10) is a two-level detection circuit consisting of resistors (5d) to (5f), a first voltage comparator (11) and a second voltage comparator (12), ( 13) is a D-type flip-flop that outputs the reset signal shown in FIG. 4(f).

In addition, the first voltage comparator (11) has a comparison voltage V! at its inverting input terminal. is input, and when the signal shown in FIG. 4(c) is input to the non-inverting input terminal, and the magnitude of this input signal is higher than the comparison voltage V, the signal shown in FIG. 4(e) is output. . Further, the second voltage comparator (12) has a non-inverting input terminal inputted with a comparison voltage vI, and an inverting input terminal inputted with a comparison voltage vI (see FIG. 4).
When the signal shown in c) is input, the magnitude of this input signal is the comparison voltage V! When the temperature becomes low, the signal shown in FIG. 4(d) is output.

Next, the operation of the abnormality detection device having the above configuration will be explained with reference to FIGS. 4(11) to 4(f). First, at time t when the microcomputer (1) is operating in a normal state. to time t1, the microcomputer (1
) from the output terminal (1a) to the path (7) shown in Fig. 4(a).
is this oscillation signal, resistor (5a) and capacitor (6
The exclusive OR sign with the signal delayed by a) is “H”
During the level, the transistor (9) is not conductive and the capacitor (6b) charges an electric charge through the resistor (5b) and the transistor (9) which is conductive. and,
When the above output signal reaches the rLJ level, the transistor (
9) is not in a cut-off state, and the charge in the capacitor (6b) is discharged through the resistor (5c).

Thereafter, the above-described operation is repeated, and the integrating circuit (8) outputs the output signal shown in FIG. 4(c). Here, the output voltage of the integrating circuit (8) generated at each time To is the comparison voltage v1
Since the first voltage comparator (11) does not output any output signal as shown in FIG. 4(e), the second voltage comparator (12) )
does not output any output signal as shown in FIG. 4(d). Therefore, the output signal of the second voltage comparator (12) is input to the set terminal S of the D-type flip-flop (13), and the output signal of the first voltage comparator (11) is input to the data input terminal. , since the output signal of the exclusive OR circuit ('7) is input to the trigger input terminal T, its output terminal Q
is maintained at "L-level". Therefore, the reset circuit (3) does not generate a reset signal, and the microcomputers (1) and (7) continue to operate normally. Next, at time 1, the microcomputer (1) and (7) continue to operate normally. If an abnormality occurs in the sequential operation of (1) for some reason, the period of the oscillation signal output from the output terminal (la) of microcomputer (1) will be as shown in Figure 4 (a). When the period TI becomes shorter than Tl, the oscillation signal with this period TI is input to the edge detection circuit (4).For this reason, this edge detection circuit (4) converts the output signal shown in FIG. 8).Therefore, the integrating circuit (8) integrates this signal, but since the charging and discharging of the charge in the capacitor (6b) is incomplete compared to the period To, the output signal is as shown in Fig. 4(c). ), the comparison voltage becomes higher than the comparison voltage v2.Therefore, this output signal is input to the non-inverting input terminal of the first voltage comparator (11) and is also input to the inverting input terminal of the second voltage comparator (12). do.

Therefore, the first voltage comparator (11) outputs the output signal shown in FIG. 4. As shown in FIG. 4(d), no output signal is output.

For this reason, the D-type flip-flop (13) is set 8), and rH is output from its output terminal Q as shown in Fig. 4(f).
Outputs a J level signal. Therefore, since the reset signal output from the reset circuit (3) is input to the reset terminal (1b) of the microcomputer (1),
The microcomputer (1) can be returned to normal operation. Next, at time t, if an abnormality occurs in the sequential operation of the microcomputer (1) for some reason, the period of the oscillation signal output from the output terminal (1a) will be as shown in FIG. 4(a). When the period T2 becomes long as shown in FIG.
). Therefore, this edge detection circuit (4) outputs the signal shown in FIG. 4 to the integration circuit (8). Therefore, the integrating circuit (8) integrates this signal, but since the charge and discharge of the capacitor (6b) is complete compared to the period To, the output signal is as shown in FIG. 4(c).
The comparison voltage V does not become very high. Therefore, the output signal is input to the non-inverting input terminal of the first voltage comparator (11) and also input to the inverting input terminal of the second voltage comparator (12). Therefore, the first voltage comparator (11) does not output any output signal as shown in FIG. 4(e), but the second voltage comparator (12) outputs no output signal as shown in FIG. 4(d). is output to the set terminal S of the D-type flip-flop (13). Therefore, the output terminal Q of this D-type flip-flop (13) maintains the "H" level as shown in FIG. 4(f). Therefore, since the reset signal output from the reset circuit (3) is input to the reset terminal (1b) of the microcomputer (1), the microcomputer (1) can be returned to normal operation.

In addition, in the above description, the period T of the oscillation signal output from the output terminal (1a) of the microcomputer (1).

The case where the period is as short as T1 or as long as the period Tz has been described, but it goes without saying that the same thing can be done when the oscillation signal stops. In addition, when the operation of the microcomputer (1) completely stops, the operation is incomplete, and the period of the oscillation signal output for monitoring is outside the predetermined period, it is accurately detected, The microcomputer (1) can be reset,
It is possible to restore normal operation. Furthermore, although the above-described embodiments have been described with respect to a microcomputer, it goes without saying that the same can be applied to a processing device that executes serial input processing in a time-series manner using a stored program method.

As described above in detail, the abnormality detection device according to the present invention can quickly and accurately detect abnormalities in microcomputers and other processing circuits, quickly escape from abnormal operation, and operate normally. This has the effect of increasing the reliability of the entire device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional abnormality detection device, FIGS. 2(a) to 2(c) are diagrams showing waveforms of each part in FIG. 1,
FIG. 3 is a circuit diagram showing an embodiment of the abnormality detection device according to the invention, and FIGS. 4(a) to 4(f) are diagrams showing waveforms of various parts in FIG. 3. (1)・Fist...Microcomputer, (1a)...
・Output terminal, '(lb)...Reset terminal, (2)
... Abnormality detection circuit, (3) ... Reset circuit,
(11) (4) Edge detection circuit, (5a) to (5f)
...Resistor, (6a) and (6b)...Capacitor, (7)...Exclusive logic circuit, (8)...轡-integrator circuit, (9)...Transistor, ( 10)...
・2 level detection 10 paths, (11)...-first voltage comparator, (12)...second voltage comparator, (13)...
・D-type flip-flop. In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa (12) Figure 1 Figure 2 Commissioner of the Japan Patent Office 1. Indication of the case Japanese Patent Application No. 114825/1982 2, title of the invention Abnormality detection device 3, person making the amendment Relationship to the case Patent applicant address Hyogo Prefecture, Himeji-type Tsuchiyama-5-15 Name Comprehensive automobile safety pollution Technical Research Association Representative Tatsu Minamiguchi Department 4, Agent address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, Subject of amendment (1) Detailed description of the invention in the specification column 5, Contents of amendment ( 1) On page 10, lines 15 and 16 of the specification, "because the charging and discharging of the electric charge is complete compared to the period T." is corrected to "because the discharging of the electric charge is longer than the period To." . (21 Ibid., page 13, line 3, "exclusive logic circuit" is corrected to "exclusive OR circuit". (3) Figure 1 of the drawings is corrected as shown in the attached sheet.

Claims (1)

[Claims] Performs arithmetic processing in time series according to a pre-programmed procedure, detects the edges of the output signal of a predetermined period generated from the processing device according to the above program, and generates a pulse signal with a predetermined pulse width for each edge. an edge detection circuit that integrates the output of this edge detection circuit; a two-level detection circuit that determines whether the output voltage of this integration circuit is within a predetermined set voltage range; An abnormality detection device comprising: a reset circuit that receives the output of the circuit and repeatedly supplies a reset signal at regular intervals to the processing device when the output of the integration circuit is outside a predetermined set voltage range. .