JPS6051317A - Voltage detecting circuit of mos integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a power source voltage detecting circuit which is stable against a variance of temperature, by using an MOS transistor TR, which is not subjected to channel doping, as a TR which detects a potential with a treshold. CONSTITUTION:For the purpose of lessening the variance of a detection voltage due to a change of temperature, R2/R1 is set to a small value, and the threshold of a TRT1 is set to a high value. In case of channel doping, the part of the TR T1 is masked to perfrom channel doping for a P-channel TR except the TRT1, and the threshold is reduced. If a bulk MOSTR which is not subjected to channel doping is used as the TRT1, the power source voltage detecting circuit which is relatively stable against a variance of temperature is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a voltage detection circuit in a MOS-IC.

<Prior art> The field of application of MOS-LSI has expanded greatly in recent years.
The specifications for rc are also becoming more complex and diverse. Particularly in the field of control equipment, it is often required that ICs do not operate abnormally even below the operating range of the IC. In such a case, it is necessary to provide a power supply voltage detection circuit within the IC and take measures such as resetting the IC internally or prohibiting the output of the IC when the power supply voltage is below a certain level.

It is difficult to create a reference voltage for detecting the power supply voltage inside the MO5IC, and therefore a stable power supply voltage detection circuit cannot be realized with a simple circuit. Especially I
In a simple voltage detection circuit, the detection level will vary greatly due to variations in the Devine parameters within the IC due to variations in C manufacturing.

FIG. 1 shows a conventional voltage detection circuit. Here, D is a diode, T+, T2 is a P-channel transistor, and T3
is an N-channel transistor, and R1+R2 and R3 are resistors. In a standard CMO8 IC, the P-channel transistors and N-channel transistors within the chip have the same threshold voltage within each group. That is, all P-channel transistors have the same threshold voltage (Vthp), and all N-channel transistors have the same threshold voltage (Vthp).
The channel transistors are at the same threshold voltage (Vthn). Therefore, T, , T2 in Fig. 1
The threshold voltages of are generally the same.

In the circuit of FIG. 1, the diode D is used for the purpose of reducing fluctuations in the power supply voltage detection level due to temperature changes in the threshold voltage of T1.

The operating principle of FIG. 1 is shown in FIG. 2.

To simplify the explanation, let us assume that the voltage gain of the inverter (INV+, abbreviated as J, the same below) consisting of T, , R3 is infinite, that is, the power supply voltage ([VDD, abbreviated as J, the same below) and 0. Potential difference between points (VDD-1Vthp+I)
is the threshold voltage of T1 (r I Vthp+
Abbreviated as IJ. It is assumed that when the following conditions occur, T1 is turned off and the potential at the 0 point is at the ground (GND) level, and when the following conditions occur, T1 is turned on and the potential at the 0 point is at the VDD level.

When VDD is raised from O, the potential at the 0 point is shown in Figure 2.
It changes like this. FIG. 2 also shows changes in VDD I and Vthpl I when VrlD increases from O. In Figure 2, ■ and VDD -IVthp+1
If VDD is higher than the power supply voltage (VDD, ) where
.

If it is lower, the 0 point becomes the GND level.

On the other hand, T2. The input inversion voltage of the inverter (abbreviated as "■N■2", the same applies hereinafter) consisting of T3 is approximately VD vertical υ
, which is shown in broken lines in FIG.

As can be seen from Figure 2, when VDD < VDD, the potential at the 0 point is 0, which is lower than the inversion voltage of NV2, so the potential at the 0 point in Figure 1 is at the VDD level, and when VDD > VDD, the potential at the 0 point is 0. Since is VDD and is higher than the inversion voltage of INV2, the potential at the 0 point becomes the GND level. Therefore, by controlling the logic circuit using the output signal at point 0, V
It is possible to prevent the logic circuit from malfunctioning at VDD below Dr)+.

Let's now look at VDD using a simple formula.

The potential vA at point 0 is as follows. Here, VF is the forward voltage of diode D.
voltage.

On the other hand, the potential VA1 at point A where the NVI inverts the output is (A) VAI = VDD - I Vthp+ 1 (2), (1), (2+ from VDD (7) detection level)
vvDDl is obtained by solving . When IVthp+l changes, the VDD detection level (vvDD) changes as follows.

From (4), the minimum value of DD'A IVthp+I is 1
(When R2-〇). In other words, if the VDD detection level /l/VDD is set to 1Vthp+1, 1Vth
VDD changes by the amount that p+I changes.

Generally, in a CMOS circuit, in order to operate the circuit stably, it is necessary to select IVthp I +Vthn < VDD (5), and the aforementioned VDD detection level is set to IVthp +
Choosing l is practically meaningless because other logic circuit sections will not operate stably.

Considering the normal operating range of C/MO8I C from 2.5v to 6v, Vthp l and Vthn are each approximately I
V[It is normal to choose. Further, vF of the diode D is approximately 0.7V in the case of a silicon substrate. Now l
Vthp+l=1. Ov, Vp = 0.7
If the design is made so that the power supply voltage detection level VDD is 2.7 V at V, then the formula (3) is as follows: Vthp I is 1. Assuming that it fluctuates at Ov±0.1v, the power supply detection level is 2.03 Vmin,
2.7 V type.

3.36 Vmax, which is a variation of ±24% with respect to the design center.

In the mass production of MO5ICs, it is common for the transistor threshold voltage to vary by ±0.1V, so it is extremely difficult to stabilize the power supply detection level using the circuit shown in FIG.

<Object of the Invention> The object of the present invention is to improve the stability of the VDT output level using the simple circuit shown in FIG.

<Example> From equation (4), VDIl due to variation of 1Vthp+1
It can be seen that in order to reduce the variation in l+, it is sufficient to reduce R2/R1. In order to obtain the same VDD by reducing R2/R1, 1Vthp+l must be increased. However, due to the relationship in equation (5), 1Vthpl of the entire IC cannot be increased. Therefore, the problem can be solved by increasing only 1Vthpl of T1 in FIG. Now, let l vthp 1 of T in FIG. 1 be 1.
5v, 1Vthpl in the same IC to 1. Assume that Ov is Nishi. From equation (3), if VDD is designed to be 2.7V, then q = b.

As mentioned above, assuming that IVthp+I varies by ±0.1■, the detection level of the power supply voltage is 2.45vm.
in.

2.70 Vtyp and 2.95vmax, which is an error of ±9% with respect to the design center value.

Normally, in a P-well C/Wt OS using an N substrate, the substrate has a specific resistance of 3 to 6 ΩG and a crystal orientation of <10<)>.
The IVt of the P-channel transistor with a gate oxide film of 800 to 1000 A is used.
hpl is approximately 1.5v. In order to satisfy the above-mentioned equation (5), ions called channel doping are implanted into the gate portion of the P-channel transistor, and l Vth
It is normal to lower p l.

Therefore, when performing this channel doping, masking the portion 13 in FIG. 1, channel doping is performed on the P channel transistors other than T (T2 in FIG. 1) to lower l Vthp l. That is, by using a bulk (substrate) MOS transistor with no channel doping as T1, a relatively stable power supply voltage detection circuit can be achieved even with a simple circuit as shown in FIG. In addition, P
Channel tV) Channel doping of a transistor is normally performed using a photomask and ions are implanted only into the gate portion of the transistor, so this method in which channel doping is not performed only in the T1 portion can be easily implemented without changing the process.

<Effects> As described above in detail, according to the present invention, a stable voltage detection circuit can be obtained with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a voltage detection circuit, and FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1. Explanation of symbols D: diode, 'r', 'r2: r' channel transistor, T3: N channel transistor, R,, R
2, R3: resistance.

Claims (1)

[Claims] 1. In MOS-IC, MO is characterized in that it is constructed using a transistor using a substrate (bulk).
Voltage detection circuit in S-IC.