JPS6051151B2 - デ−タ処理システム - Google Patents

デ−タ処理システム

Info

Publication number
JPS6051151B2
JPS6051151B2 JP55031490A JP3149080A JPS6051151B2 JP S6051151 B2 JPS6051151 B2 JP S6051151B2 JP 55031490 A JP55031490 A JP 55031490A JP 3149080 A JP3149080 A JP 3149080A JP S6051151 B2 JPS6051151 B2 JP S6051151B2
Authority
JP
Japan
Prior art keywords
bus
signal
information
nexus
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55031490A
Other languages
English (en)
Japanese (ja)
Other versions
JPS55134427A (en
Inventor
ポ−ル・ビンダ−
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of JPS55134427A publication Critical patent/JPS55134427A/ja
Publication of JPS6051151B2 publication Critical patent/JPS6051151B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
JP55031490A 1979-03-12 1980-03-12 デ−タ処理システム Expired JPS6051151B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1935179A 1979-03-12 1979-03-12
US19351 1979-03-12

Publications (2)

Publication Number Publication Date
JPS55134427A JPS55134427A (en) 1980-10-20
JPS6051151B2 true JPS6051151B2 (ja) 1985-11-12

Family

ID=21792737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55031490A Expired JPS6051151B2 (ja) 1979-03-12 1980-03-12 デ−タ処理システム

Country Status (10)

Country Link
JP (1) JPS6051151B2 (it)
AU (1) AU542538B2 (it)
BR (1) BR8001527A (it)
CA (1) CA1143853A (it)
DE (1) DE3009529A1 (it)
ES (1) ES489424A0 (it)
FR (1) FR2451601A1 (it)
GB (1) GB2044967A (it)
IT (1) IT1129639B (it)
SE (1) SE8001908L (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU576348B2 (en) * 1984-02-29 1988-08-25 Measurex Corporation Processing information
US4669056A (en) * 1984-07-31 1987-05-26 International Business Machines Corporation Data processing system with a plurality of processors accessing a common bus to interleaved storage

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2997896A (en) * 1958-10-08 1961-08-29 Preston Martin Variable speed drives
US3999170A (en) * 1975-01-08 1976-12-21 Hewlett-Packard Company Multiple access interconnect system
DE2846488A1 (de) * 1977-10-25 1979-05-03 Digital Equipment Corp Datenverarbeitungssystem

Also Published As

Publication number Publication date
DE3009529A1 (de) 1980-09-25
JPS55134427A (en) 1980-10-20
FR2451601A1 (fr) 1980-10-10
SE8001908L (sv) 1980-09-13
BR8001527A (pt) 1980-11-11
ES8103407A1 (es) 1981-02-16
AU542538B2 (en) 1985-02-28
ES489424A0 (es) 1981-02-16
CA1143853A (en) 1983-03-29
IT8020544A0 (it) 1980-03-12
IT1129639B (it) 1986-06-11
AU5637680A (en) 1980-09-18
GB2044967A (en) 1980-10-22

Similar Documents

Publication Publication Date Title
US4488217A (en) Data processing system with lock-unlock instruction facility
US5001624A (en) Processor controlled DMA controller for transferring instruction and data from memory to coprocessor
US3940743A (en) Interconnecting unit for independently operable data processing systems
US5119480A (en) Bus master interface circuit with transparent preemption of a data transfer operation
US4961140A (en) Apparatus and method for extending a parallel synchronous data and message bus
CA2050129C (en) Dynamic bus arbitration with grant sharing each cycle
US4030075A (en) Data processing system having distributed priority network
US5555425A (en) Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters
US4763249A (en) Bus device for use in a computer system having a synchronous bus
US5535341A (en) Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation
US4706190A (en) Retry mechanism for releasing control of a communications path in digital computer system
US4661905A (en) Bus-control mechanism
US4209839A (en) Shared synchronous memory multiprocessing arrangement
JPS60186956A (ja) デジタルデ−タ処理システムの入/出力部のためのバツフア装置
JPS6112303B2 (it)
US4495564A (en) Multi sub-channel adapter with single status/address register
EP0301610B1 (en) Data processing apparatus for connection to a common communication path in a data processing system
JPS5922251B2 (ja) 多数未完情報要求を与えるシステム
JPH08255124A (ja) データ処理システムおよび方法
WO1998032063A2 (en) Method and apparatus for zero latency bus transactions
JPS5875232A (ja) 多重取出しバス・サイクル操作を与えるシステム
JPH0683763A (ja) 中央アービタをスレーブアービタに変換する方法およびシステム
US6604159B1 (en) Data release to reduce latency in on-chip system bus
JPH0198048A (ja) 周辺装置制御装置およびアダプタ・インターフェース
US5241661A (en) DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter