JPS6047680B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device used in a flat panel display device such as a liquid crystal television or an electrochromic display, and more specifically, the present invention relates to a memory device used in a flat panel display device such as a liquid crystal television or an electrochromic display. This article relates to storage devices that are improved by combining them.

For example, a laminated liquid crystal matrix panel that can generally display images including halftones is 197g1f. It is publicly known as shown in Denshi Kagaku published in June, pages 83 to 84.

Such a laminated liquid crystal matrix panel has a reinforcing plate (not shown).

On one side, a storage device called 1 transistor and 1 capacitance per pixel as shown in Figure 1 is installed for display purposes.
A seal (not shown), a liquid crystal layer (not shown), a transparent electrode (not shown), and a front glass are formed on top of the array to use one electrode of each capacitance as a reflective electrode of a liquid crystal device. It is formed by sequentially forming plates (not shown). However, according to such a laminated liquid crystal matrix panel, 1C for display
If a video signal is supplied to data bus B of cell 1 and a scanning signal is supplied to address bus A, the transistors are switched on by the scanning signal, and the video signal voltage is stored in capacitor 3 accordingly. If you have a charge voltage stored in a pixel, a blinking image can be projected on the panel according to the charge voltage; if such pixels are arranged in a matrix, for example, 240 x 24 pixels, half of the panel surface will be displayed. You can create videos that include tones. However, in the case of such a display device, the second number of pixels is, for example, 24, taking into account the resolution.
Since it is formed as 0x240 (57600), the screen size is 36 order x 48Tf0n (2.
Therefore, when forming the display device, it is necessary to form a storage device equivalent to at least 2.4 inches. Therefore, the storage device equivalent to 2.4 inches must be formed. When forming a wafer with a diameter of 75wL, only one memory chip can be manufactured, and when forming these memory cells, the step ratio of 3 to 100% per wafer is approximately 100%. - If this is not achieved, the price of the storage device described above will become very high.

In general, in the memory device shown in FIG.
In this example, one transistor 2 and one capacitor 3 are connected in series between the data bus B and the reference voltage source (earth).
And the gates of these transistors 2 are connected to the address bus A.
However, for example, if one or both of buses A and B are disconnected, buses A and B are short-circuited with other wiring, or buses A and B are connected to the base. If a short circuit occurs between them, all of the memory cells 1 involved in the shorted bus become inoperable, and a large number of pixels become inoperable.

In other words, if the data bus B1 address bus A has a mask defect for some reason or dust gets mixed in during the manufacturing process, short circuits and disconnections will occur. For example, if the number of liquid crystal pixels is arranged in a 256 x 256 array with a pitch of 300 microns each, data bus B is a 5 micron wide N+ diffusion wiring, and address bus A is a 5 micron wide aluminum wiring. The yield on the bus can be calculated as follows based on the formula for deriving the LSI yield.

That is, the yield Y of LSI is generally expressed by the following formula.
-1A
Here, DA: Defect surface density D1: Defect linear density A: Area scale 1: Line length scale By the way, D1 of the N+ diffusion layer with a width of 5 microns is also:
Dl of a 5 micron wide aluminum wiring layer is.

Therefore, the yield Y of the address bus according to the conventional configuration.

= 0.986... 1 bus (256 x 0.
Per 3TIgn.

), and in order for all 256 address buses to be of good quality, the following is true.

Also, the yield Y of the data bus according to the conventional configuration.

-M, -υ◆υGO, and therefore, the yield Y of all bus wiring according to the conventional configuration.

T becomes.

Therefore, as can be understood from the above calculation formula and results, the yield of the storage device with the conventional configuration is 0.22%, which is extremely low and the price of the product is extremely high. I was getting used to it.

The present invention relates to a storage device devised in view of the above drawbacks, and its purpose is to provide a storage device that can prevent a decrease in yield caused by mask defects or dust mixed in during the manufacturing process. It provides:

Another object of the present invention is to provide a memory device that aims to reduce the cost of chips by preventing a decrease in yield.

According to the present invention, the features include a data bus,
Two address buses are provided for each memory cell, forming a pair, and each pair of data buses and each pair of address buses are short-circuited using a bridge wire. It is.

Then, the short circuits occurring in these data buses and address buses are found through testing, and the short circuits are isolated using a desired method.The details are shown in Figures 2, 3, and 4. , an embodiment of the circuit diagram and apparatus according to the present invention shown in FIG. According to FIG. 2, the storage device is provided with a pair of data buses B and b to which the same video signal is supplied.

A pair of address buses A and a to which the same scanning signal is supplied are also provided. A bridge line 4 is formed between the pair of data buses to short-circuit data bus B and data bus b, and a bridge line 4 is formed between the pair of address buses to short-circuit address bus A and address bus a. A connecting line 5 is formed. Furthermore, a closed loop 1A having an arbitrary configuration is provided between the pair of data buses and between the pair of address buses.
, 1B data bus B, bl address bus A,
Test pads 6 and 7 are formed at portions a where bridge short circuits 4 and 5 are connected. Also, bad 6 and data bus B
, b, and between pad 7 and address bus A, a.
Fusible fuses 8 and 9 are formed between the two. In addition, the data buses B, which are arranged in a matrix,
A memory cell 10 is located at the intersection of address bus A and a.
is formed. These memory cells 10 are constructed by connecting first and third transistors 11 and 13 in series between a pair of data buses B and b, and connecting the gates of the first and third transistors 11 and 13 to the pair of data buses B and b. The fourth and second transistors 14 and 12 are connected in series between the pair of data buses B and b. The gates of the transistors are connected to the pair of address buses A and a.
By connecting to the other of the address buses a, and furthermore, the series connection point between the first transistor and the third transistor, and the series connection point between the fourth transistor and the second transistor. It is constructed by making a common connection at one point 15 and forming a capacitor 16 between the common connection point 15 and a reference voltage source (earth). If the circuit shown in FIG. 2 is specifically made into a device, the circuit shown in FIG. 3 can be obtained.

FIG. 3 shows a plan view of a selective device of a part of the circuit shown in FIG. 2.

According to the figure, data buses Bl, B formed by diffusion
2, b2, B3, b3, B4 and address buses Al, A2, a2, A3 made of aluminum are arranged in a matrix. A bridge line 5 is formed between the address bus and A2 by diffusion.
are formed, and these bridge lines 5 and address buses A2, a2
A test pad 7 is formed at the connection point (contact point) 17 between the test pad 7 and the address bus A2.
By making the aluminum wiring thinner, a view 9 is formed between the wires 2 and a2, which can be cut by laser or the like. Furthermore, memory cells 10 are formed at the intersections of address buses A2, a2 and data buses 8, B2, B3, b3. Most of the area of these memory cells 10 is occupied by the capacitor 16, and at the four corners there are first, second, third, and fourth cells whose common electrode 15 is the surface electrode of the capacitor 16. Transistors 11, 12, 13, and 14 are formed. Here, the control electrodes constituting the first and third transistors 11 and 13 are formed by extending the address bus A2, and the control electrodes are formed by extending the address bus A2, respectively. The data buses B2, b2, B3, and b3, which are formed by diffusion, are extended as they are. Further, the fourth and second transistors 14
, 12 are formed by extending the address bus A2, and the first electrodes are formed by extending the data buses B2, b2, B3, b3 formed by diffusion. According to the storage devices shown in FIGS. 2 and 3, mask defects or dust mixed in during the cutting process may cause any data bus B,
b or a short circuit in any address bus A, a;
Even if a disconnection occurs, the defective part caused by the disconnection can be removed as follows.

That is, for example, if a disconnection occurs at point α of the address line A1 shown in FIG. 2, the first and third transistors 11 and 13 in the cells 10a and 10b will no longer receive an address signal and will no longer operate.

However, in these devices, there is another pair of address lines a1 and a bridge line 5, so the bus 1
c. , 1d are working as pilot bus lines, and the cells 10a and 10b, which normally do not operate, are operated by the second and fourth transistors 12 and 14. Therefore, in these devices, as long as a bus line is formed by the address bus A and the Al bridging line 5, the cell 10 will not become defective due to disconnection. Furthermore, in these cases, a short circuit may occur at the point α of the address line A1 shown in FIG. However, if such a problem occurs, the fuses 9a, 9b
The bus line A1 can be separated from the problem short circuit by cutting with a laser.
, 1d, it is possible to eliminate the problem of short-circuit corrosion. Therefore, in the devices shown in FIGS. 2 and 3, defects due to short circuits do not occur. Note that these disconnections and short circuits can be explained in the same way for the data buses Bx and b, so their explanation will be omitted.

However, the problem with these devices is how to find the defective point α.

However, these can be easily checked by using a conventional test machine. That is, in order to facilitate the test, for the memory device 18 formed for each wafer as shown in FIG. 6, 7, and beads 8 and 9, for example, a memory cell group formed in a 256 x 256 arrangement is divided vertically and horizontally into four (divided into six magnetic parts),
They should be provided on the periphery of each block. By doing so, it is possible to form a closed loop l as shown in FIG. , 7c, 7d, conduction or non-conduction, pads 7a, 7b, 7c, 7 to the base.
If, for example, six flood mats are tested for continuity or non-continuity of d using the same electrode rod, problematic short circuits and disconnections can be easily detected. It should be noted that these inspection methods can be similarly applied to the data bus, so a description thereof will be omitted.

Incidentally, since the data bus which must have a fuse is formed by diffusion, in these devices the diffusion is cut at the fuse portion. These data buses are connected by fuses. Thus, according to the devices shown in FIGS. 2, 3, 4, and 5, it is possible to provide a memory device that can improve the yield.

The present invention will be explained using a second embodiment as shown in FIG.

FIG. 6 shows the third and fourth cells of the memory cell 10 shown in FIG.
The transistors 13 and 14 are removed.

However, even with this method, for example, a disconnection or short circuit at the point β of the address bus A1 can be compensated for by configuring the loop 1e1. If the present invention is explained using a third embodiment, it can be as shown in FIG.

FIG. 7 shows the memory cell 10 shown in FIG. 2 with the fourth transistor 14 removed, but even with these methods, it is possible to assemble the memory cell 10 in a network like manner as in FIGS. A similar closed-loop configuration can bring out similar effects.

However, in the first, second, and third embodiments, as is clear from the examples shown in the table below, cases where "memory failure" occurs are fewer in cases where the number of transistors is larger.

That is, the above table shows two address buses A,,a, and two data buses Bl,b as shown in FIG.
For l, a transistor is formed only at the intersection of address bus A and data bus B, and a transistor is formed at the intersection of address bus A and data bus A, and the intersection of address bus A and data bus A,
In addition, a transistor is configured at the intersection of address bus A and data bus bl, resulting in a two-transistor configuration.
Furthermore, a three-transistor configuration is constructed in which transistors are configured at the intersections of address bus A and data bus 2, at the intersections of address bus a and data bus h, and at the intersections of address bus A and data bus bl. , the intersection of address bus A and data bus B, address bus a
The intersection of address bus A1 and data bus B, the intersection of address bus A and data bus B, and the intersection of address bus A and data bus B.
4 with a transistor formed at each intersection with 1
The transistor configuration is used, and the rate of each cell being a good product is 7 = 15. In other words, this is a consideration of the number of transistors, but as can be seen from the table, in a one-transistor configuration, the cells that could only get 4 defects were 7116 and 8116 in 2-transistor, 3-transistor, and 4-transistor configurations, respectively. ,9116 and 3 good items.
It can be seen that the number has increased to 4 and 5.

Therefore, according to the device according to the configuration of the present invention, it is easy to understand that the improvement in the memory defect rate varies depending on the cell structure. This shows the number of cases that can be rescued compared to the previous one, and the yield improvement effect is significant.

Here, the manufacturing yield of the circuit shown in FIG. 2 with respect to the circuit configuration shown in FIG. 1 can be expressed using a calculation formula as shown below.

That is, by applying the conditions shown in Figure 1 to Figure 2, the number of memory cells is 256 x 256, they are arranged at a pitch of 300 microns, and the widths of the address bus and data bus are Assuming that the width is 5 microns, the respective yields can be calculated as follows.

First, by deriving the general formula according to the present invention, if y is the yield of a single-configuration bus as shown in FIG. 9A, then ? The yield y″ is as follows.

Further, when dualizing, the yield y'' per 1 block and 11n scale is as follows, and when dualizing as shown in FIG. 9B, the yield y* per n block and 1 scale is as follows.

Therefore, in the storage device shown in FIG.
The yield YN by the method is =0.99998
6...1 bus (256 x 0.3 TWL).

), and the yield YAN when all 256 address buses are good products is as follows.

On the other hand, if we perform the same calculation for data buses, we get that the yield Y is that all 256 data buses are good.
DN becomes.

Therefore, the yield Yh of all bus wiring according to these is:
becomes.

5 Therefore, according to the present invention, the conventional yield is reduced to 0.
Although it was 22%, it was 99.25%, and the difference is obvious at a glance.

As described above, it is possible to provide a storage device that has many advantages.

O It is clear that the present invention can be modified not only in the embodiments presented herein but also within the scope of the claims.

For example, in the storage devices shown in FIGS. 2, 6, and 7, the bridge lines and pads are formed in blocks.
However, if the complexity of the test and the number of fuse blowouts are out of the question, they may be provided for each cell as shown in Figure 8, or fuses made of polysilicon, etc. But that's fine. Furthermore, the pads, fuses, and bridge lines may be formed only on either the address bus or the data bus. Furthermore, the bus drive circuit may be built-in or external.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional storage device, FIG. 2 is a circuit diagram of a first embodiment of the present invention, and FIG. 3 is a plan view of a part of the circuit shown in FIG. , FIG. 4 is a diagram of a state in which the device of the present invention is built into a wafer, FIG. 5 is a partial circuit diagram for explaining the present invention, and FIG. 6 is a circuit diagram of a second embodiment of the present invention. , FIG. 7 is a circuit diagram of a third embodiment of the present invention, FIG. 8 is a circuit diagram of a fourth embodiment of the present invention, and FIGS. 9A and 9B are explanatory diagrams used for yield calculation. 1, 1c, 10, 10a, 10b...memory cell, 2...transistor, 11...first transistor, 12...second transistor , 13...Third transistor, 4...Fourth transistor
Transistor, 3, 16... Capacitor, 4,
5...Bridging wire, 6,7...Test pad, 8,9...Fuse.

Claims (1)

[Claims] 1. In a memory device having a pair of data buses and a pair of address buses for one memory cell, a bridge line is provided between one or both of the pair of data buses and the pair of address buses. A storage device characterized in that: 2. A storage device according to claim 1, characterized in that a data bus and an address bus are provided with test pads. 3. A storage device according to claim 2, characterized in that a fuse is provided between the data bus and the test pad and at least one between the address bus and the test pad. 4. A storage device according to claim 1, characterized in that a bus drive circuit formed on the same basis is connected to the data bus and the address bus. 5. In the storage device according to claim 1, the memory cell structure is arranged between the first and second data buses between the pair of data buses.
transistors are connected in series, the gate of the first transistor is connected to one of the pair of address buses, and the gate of the second transistor is connected to one of the pair of address buses. the first transistor and the second transistor.
A storage device characterized in that a capacitor is formed between a common connection point with the transistor and a reference voltage source. 6. In the storage device according to claim 5, the gate electrode of the first transistor or the second transistor is connected to one of the pair of address buses, or A memory device characterized in that a third transistor connected to an address bus is connected in parallel. 7. In the storage device according to claim 1, the memory cell structure is arranged between the first and third data buses.
transistors are connected in series, and the first,
The gate of the third transistor is connected to one of the pair of address buses, and the second and fourth transistors are connected in series between the pair of data buses. 2. The gate of the fourth transistor is connected to the other address bus of the pair of address buses, and the series connection point between the first transistor and the third transistor, and the second transistor and the fourth transistor are connected. A memory device characterized in that series connection points with transistors are commonly connected, and a capacitor is formed between the common connection points and a reference voltage source.