JPS6039261A - Memory fault restoration system - Google Patents

Memory fault restoration system

Info

Publication number
JPS6039261A
JPS6039261A JP58147756A JP14775683A JPS6039261A JP S6039261 A JPS6039261 A JP S6039261A JP 58147756 A JP58147756 A JP 58147756A JP 14775683 A JP14775683 A JP 14775683A JP S6039261 A JPS6039261 A JP S6039261A
Authority
JP
Japan
Prior art keywords
data
mem
active
memory device
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58147756A
Other languages
Japanese (ja)
Inventor
Shigeru Takano
茂 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58147756A priority Critical patent/JPS6039261A/en
Publication of JPS6039261A publication Critical patent/JPS6039261A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To use a memory device of an active system while restoring automatically the memory if a temporary parity check fault is generated because of a software error by writing simultaneously a data from an active or spare system processor to the active system and spare system memory devices at all times. CONSTITUTION:Data are written simultaneously from the active system and spare system processors CPU#0 and CPU#1 to the active system and spare system memory devices MEM#0 and MEM#1 at all times. Thus, the MEM#0 and MEM#1 store the same data at the normal operation. An address register A- REG#0 of the active system and a data check circuit D-CHECK#0 of the active system are connected to the CPU#0 and the MEM#0 and the MEM#1 is connected to the check circuit. Further, the data from the MEM#1 is fed to the CPU#0 via the data register D-REG#0 of the active system to the active system detecting a momentary error to restore and use the MEM#0 automatically.

Description

【発明の詳細な説明】 （ａ）１発明の技術分野 本発明はメモリ障害修復方式に係り、特に現用系及び予
備系からなる二重化されたメモリ装置に於けるメモリ障
害修復方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) 1. Technical Field of the Invention The present invention relates to a memory fault recovery method, and more particularly to a memory fault recovery method in a duplex memory device consisting of an active system and a standby system.

（ｂ）、従来技術の問題点 ディジタル電子交換機等に於いてはシステムの安定度を
向上する為、現用系及び予備系からなる二重化されたシ
ステムを採用する場合が多い。(b) Problems with the Prior Art In digital electronic exchanges and the like, in order to improve the stability of the system, a duplex system consisting of a working system and a standby system is often adopted.

此の様な場合従来技術に依ると現用系の処理装置が同じ
現用系のメモリ装置を読み出した時パリティ・チェソク
不良等の故障を検出した場合には、処理装置もメモリ装
置も含めて全部現用系から予備系に切り替え、以後の動
作は予備系の機器により運転され、故障した現用系のメ
モリ装置は点検修理の上手動操作によりメモリの内容を
修正していた。In such a case, according to the conventional technology, if a failure such as a parity check failure is detected when the current processing device reads out the same current memory device, all of the processing devices and memory devices, including the current processing device, are read out from the current memory device. The main system was switched to the standby system, and subsequent operations were operated by the standby system's equipment, and the malfunctioning active system's memory device was inspected and repaired, and the contents of the memory were manually corrected.

然しなから半導体メモリ装置で問題となっているソフト
・エラー等の原因で一時的にパリティ・チェックの不良
が発生している場合には、再び読み出す時は合格となる
確率が大であり、手動操作によってデータを修復し、再
び現用系にもどすのは手間がかかり、−回のパリティ・
チェックの不良で予備系に切り替えるのはシステムの運
用上不適切であると云う欠点がある。However, if a parity check has temporarily failed due to a soft error, which is a problem with semiconductor memory devices, there is a high probability that the parity check will pass when read again. It takes a lot of effort to repair the data through operations and restore it to the active system, and the parity and
The disadvantage is that switching to the standby system due to a defective check is inappropriate for system operation.

（Ｃ）８発明の目的 本発明の目的は従来技術の有する上記の欠点を除去し、
瞬間的に発生ずるエラー等に対しては自動的に現用系の
メモリ装置を修復して使用し、予備系に切り替えないメ
モリ障害修復方式を提供することである。(C)8 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
To provide a memory failure repair method that automatically repairs and uses a working memory device in response to an error that occurs instantaneously, and does not switch to a standby memory device.

（ｄ）９発明の構成 」二記の目的は本発明によれば、現用系及び予備系から
なる二重化されたメモリ装置を使用するシステムに於い
て、前記メモリ装置を読み出す時は現用のアドレス・レ
ジスタにより前記現用系及び予備系のメモリ装置を同時
に読み出し、且つ前記現用系メモリ装置のデータ・チェ
ック回路がｇｆｅ　Ｃ’ｊ出しデータの誤りを検出した
場合、前記現用のアドレス・レジスタにより前記予備系
メモリ装置から読み出したデータを保持する現用のｌ／
レジスタ回路具備し、前記現用のレジスタ回路に保持さ
れているデータにより前記現用系メモリ装置のデータを
修復することを特徴とするメモリ障杏修ｉ夏方式を提供
することにより達成される。According to the present invention, in a system using a dual memory device consisting of a working system and a standby system, when reading the memory device, the current address If the register reads out the current and backup memory devices simultaneously, and the data check circuit of the current memory device detects an error in the gfe C'j output data, the current address register reads the backup memory device. The current l// that holds data read from the memory device.
This is achieved by providing a method for repairing memory faults, which includes a register circuit and is characterized in that data in the current memory device is repaired using data held in the current register circuit.

（ｅ）０発明の実施例 図は本発明の一実施例を示すブロック図である。(e) 0 Examples of the invention The figure is a block diagram showing one embodiment of the present invention.

図中、ＣＰＵ＃０は現用系のプロセッサ、ＣＰＵ＃１は
予備系のプロセッサ、ＭＥＭ＃Ｏは現用系メモリ装置、
ＭＥＭ＃１は予備系メモリ装置、Ｄ−ＣＨＥ　ＣＫ　＃
　０は現用系のデータ・チェック回路、Ｄ−ＣＨＥＣＫ
＃１は予備系のデータ・チェック回路、Ａ−ＲＥＧ＃０
は現用系のアドレス・レジスタ、Ａ−ＲＥＧ＃１は予備
系のアドレス・レジスタ、Ｄ−ＲＥＧ＃０は現用系のデ
ータ・レジスタ、Ｄ−ＲＥＧ＃１は予備系のデータ・レ
ジスタである。In the figure, CPU #0 is the active processor, CPU #1 is the backup processor, MEM#O is the active memory device,
MEM #1 is a spare memory device, D-CHE CK #
0 is the active system data check circuit, D-CHECK
#1 is a backup data check circuit, A-REG#0
is an active system address register, A-REG#1 is a protection system address register, D-REG#0 is an active system data register, and D-REG#1 is a protection system data register.

以下図に従って本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

（１）現用系メモリ装置ＭＥＭ＃Ｏ及び予備系メモリ装
置ＭＥＭ＃ｌは現用系又は予備系のプｉコセソザにより
常に同時にデータを書込まれる。従って正常動作の場合
には常に両メモリ装置は同一の記憶内容を保持する。(1) Data is always written into the active memory device MEM#O and the backup memory device MEM#l simultaneously by the active memory device or the backup processor. Therefore, in normal operation, both memory devices always hold the same storage content.

（２）現用系のプロセッサＣＰＵ＃Ｏが本発明に依るメ
モリ装置を読み出す時は、希望データのアトルスを現用
系のアドレス・レジスタＡ−ＲＥＧ＃０に人力し、先づ
現用系メモリ装置ＭＥＭ＃０を読み出し、同時に現用系
のプロセッサＣＰＵ＃０ば現用系のアトルス・レジスタ
Ａ−ＲＥＧ＃０に基づき予備系メモリ装置ＭＥＭ＃１を
読み出ず。(2) When the active system processor CPU#O reads out the memory device according to the present invention, it inputs the desired data atlus into the active system address register A-REG#0, and first reads the current system memory device MEM#. 0, and at the same time, the active system processor CPU#0 does not read the spare system memory device MEM#1 based on the active system atlus register A-REG#0.

（３）現用系メモリ装置ＭＥＭ＃０から読み出したデー
タは現用系のデータ・チェック回路Ｄ−ＣＨＥＣＫ＃０
に於いてパリティ・チェック等のチェックを行う。同様
に予備系メモリ装置ＭＥＭ＃１から読み出したデータは
予備系のデータ・チェック回１２８　Ｄ　−ＣＨＥ　Ｃ
Ｋ　＃　１に於いてパリティ・チェック等のチェックを
行う。チェックの結果合格であれば、現用系のデータ・
チェック回路Ｄ　−ＣＨＥＣＫ＃０の内容を現用系のプ
ロセッサＣＰＵ＃０に出力する。予備系では現用のデー
タ・レジスタＤ−ＲＥＧ＃０に出力する。(3) The data read from the active memory device MEM#0 is processed by the active data check circuit D-CHECK#0.
Checks such as parity check are performed in the process. Similarly, the data read from the spare memory device MEM#1 is sent to the spare system data check circuit 128 D - CHE C
Checks such as parity check are performed in K#1. If the check results pass, the current data
Check circuit D - Outputs the contents of CHECK#0 to the active processor CPU#0. In the standby system, it is output to the current data register D-REG#0.

若し現用系のデータ・チェック回路Ｄ　−ＣＨＥ　ＣＫ
＃０に於いて誤りを検出した時は現用のプロセッサＣＰ
Ｕ＃Ｏに通知する。尚予備系のデータ・チェック回路Ｄ
　−ＣＨＥ　ＣＫ　＃　１に於いて誤りを検出した時は
予備のプロセッサＣＰＵ＃１に通知し、警報を出す。If the current data check circuit D -CHE CK
When an error is detected in #0, the current processor CP
Notify U#O. In addition, the data check circuit D of the standby system
- When an error is detected in CHE CK #1, it is notified to the spare processor CPU #1 and an alarm is issued.

（４）現用のプロセッサＣＰＵ＃０は前記の様にして保
持された現用のアドレス・レジスタＡ−ＲＥＧ＃０及び
現用のデータ・レジスタＤ−ＲＥＧ＃０の内容に基づき
、現用系メモリ装置ＭＥＭ＃Ｏのデータを修復し、再び
現用系メモリ装置ＭＥＭ＃０のデータを読み出し、デー
タ・チェック回路Ｄ−ＣＨＥＣＫに於いてパリティ・チ
ェック等のチェックを行って合格ならば出力する。(4) The current processor CPU#0 uses the current memory device MEM# based on the contents of the current address register A-REG#0 and the current data register D-REG#0 held as described above. The data in O is repaired, the data in the active memory device MEM#0 is read out again, and the data check circuit D-CHECK performs a check such as a parity check, and if it passes, it outputs.

以上述べた操作を読み出しルーチンに含めることにより
常に信頼度の高いデータを利用出来る。By including the operations described above in the reading routine, highly reliable data can always be used.

（ｆ）０発明の効果 以上詳細に説明した様に本発明によれば、ソフト・エラ
ー等の原因で一時的にパリティ、チェック不良を発生し
ている時等の場合には現用系から予備系に切り替えるこ
とな（、現用系のメモリ装置を自動的に修復して使用出
来ると云う大きい効果がある。(f) 0 Effects of the Invention As explained in detail above, according to the present invention, when a temporary parity or check failure occurs due to a soft error, etc. It has the great effect of automatically repairing and using the current memory device without having to switch to the current memory device.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例を示すブロック図である。 図中、ＣＰＵ＃０は現用系のプロセッサ、ＣＰＵ＃１は
予備系のプロセッサ、ＭＥＭ＃Ｏは現用系メモリ装置、
ＭＥＭ＃１は予備系メモリ装置、Ｄ−ＣＩ（Ｅ　ＣＫ　
＃　Ｏは現用系のデータ・チェック回路、Ｄ　−ＣＨＥ
　ＣＫ　＃　１は予備系のデータ・チェック回路、Ａ−
ＲＥＧ＃Ｏは現用系のアドレス・レジスタ、Ａ−ＲＥＧ
＃１は予備系のアドレス・レジスタ、Ｄ−ＲＥＧ＃０は
現用系のデータ・レジスタ、Ｄ　−ＲＩＥ　Ｇ　＃　１
は予備系のデータ・レジスタである。The figure is a block diagram showing one embodiment of the present invention. In the figure, CPU #0 is the active processor, CPU #1 is the backup processor, MEM#O is the active memory device,
MEM#1 is a spare memory device, D-CI (ECK
#O is the active data check circuit, D-CHE
CK #1 is a backup data check circuit, A-
REG#O is the active system address register, A-REG
#1 is a spare address register, D-REG #0 is an active data register, D-RIE G #1
is a spare data register.

Claims (1)

【特許請求の範囲】[Claims] 現用系及び予備系からなる二重化されたメモリ装置を使
用するシステムに於いて、前記メモリ装置を読み出す時
は現用のアドレス・レジスタにより前記現用系及び予備
系のメ千す装置を同時に読み出し、且つ前記現用系メモ
リ装置のデータ・チェック回路が読み出しデータの誤り
を検出した場合、前記現用のアドレス・レジスタにより
前記予備系メモリ装置から読み出したデータを保持する
現用のレジスタ回路を具備し、前記現用のレジスタ回路
に保持されているデータにより前記現用系メモリ装置の
データを修復することを特徴とするメモリ障害修復方式
。In a system using a dual memory device consisting of an active system and a backup system, when reading the memory device, the current system and the backup system are simultaneously read out using the address register of the current system, and If the data check circuit of the active memory device detects an error in the read data, the current address register is provided with a current register circuit that holds the data read from the backup memory device, and the current register is A memory failure repair method characterized in that data in the active memory device is repaired using data held in a circuit.
JP58147756A 1983-08-12 1983-08-12 Memory fault restoration system Pending JPS6039261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58147756A JPS6039261A (en) 1983-08-12 1983-08-12 Memory fault restoration system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58147756A JPS6039261A (en) 1983-08-12 1983-08-12 Memory fault restoration system

Publications (1)

Publication Number Publication Date
JPS6039261A true JPS6039261A (en) 1985-03-01

Family

ID=15437441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58147756A Pending JPS6039261A (en) 1983-08-12 1983-08-12 Memory fault restoration system

Country Status (1)

Country Link
JP (1) JPS6039261A (en)

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