JPS6033483Y2 - data display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that uses a data bus of a computer to transfer and display data independently of computer processing.

When a computer is used for data collection, analog signals from multiple sensors are converted into digital signals through an A/D converter and input to the CPU.

Normally, data input to the CPU is often displayed on a panel for human monitors.

When data input to a CPU through an A/D converter or the like is displayed using a numeric display element or the like in order to be monitored by a human system, several circuits are used.

The circuit shown in FIG. 1 is one example, in which each A/D converter 1 is installed at a location away from the human monitor or the CPU, and the digital signal line 2 is wired close to the CPU 6.
A gate 4 is provided for connecting it to the display 3 and the data bus 5 of the CPU 5.

In this method, the CPU 3 does not need to perform any processing on the display 3, and the display 3 operates independently of the operation of the CPU 5.

However, since the digital signal lines 2 for transmitting the output data of each A/D converter 1 are all routed to the CPU 6, there is a drawback that the amount of digital signal lines is increased.

Fig. 2 improves the circuit shown in Fig. 1 by extending the CPU data bus 5 to the output of each A/D converter 1, and reducing the amount of wiring from the CPU data bus line. We will show you how to reduce the number of lines.

However, in this case, since the display 3 is placed on the A/D converter side, there is a drawback that the display is far away from the human monitor or the CPU.

Therefore, it is conceivable to provide a display on the CPU side, but in this case, a display 3 is placed on the data bus 5 as shown in FIG.
It is necessary to connect it and display it using software processing.

In this method, since the independence of the display device 3 from the CPU 5 is not maintained, there is a drawback that input data cannot be confirmed if a malfunction of the CPU 6 is suspected.

This invention was made to solve the drawbacks of each of the above methods, and therefore, the purpose of this invention is to reduce the amount of wiring,
Another object of the present invention is to provide a novel data display circuit having a display section that operates independently of the operation of the CPU.

The above-mentioned object of the present invention is to provide an A
A data bus of the CPU connected to a gate circuit provided on the output side of the /D converter etc. and a data bus of the A/D converter connected to the gate circuit provided on the output side of the A/D converter etc. when the CPU is not inputting data from the A/D converter etc. an address signal generation circuit that generates an address signal for selecting one address; and an address signal generation circuit provided at a connection point on the CPU side of the data bus and closes a gate when the CPU is not inputting data from the A/D converter or the like. a second gate circuit; a latch circuit connected to the input side of the second gate circuit and latching data output to the data bus from an A/D converter selected by the address signal; It is distantly related to a data display circuit characterized by comprising a pulse generation circuit that sends a pulse to the latch circuit in synchronization with the generation of the data, and a display circuit that displays the data latched in the latch circuit. .

That is, according to the present invention, each A/
A gate circuit is provided at the output of the D converter, and a data bus from the CPU is connected to the output side of the gate circuit to input data to the CPU.

On the other hand, a second gate circuit is provided in the middle of the data bus line of the CPU, and the bus from each A/D converter is connected to the CPU during a period when the CPU is not inputting data from each A/D converter.
The A/D converter can be disconnected from the U bus, and using this period, the control section consisting of an oscillator and a counter circuit, etc., sequentially specifies each A/D converter, and transmits data using the data bus. , by holding data in a latch circuit connected to the input of the second gate circuit, the CP
The display function can be obtained completely independently of the processing of U.

As described above, since data for display is transferred using the time when the CPU is not inputting data, the display function can be obtained independently of the operation of the CPU.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a system diagram showing one embodiment of the present invention, and FIG. 5 is a block diagram showing in detail one embodiment of the control circuit which is the main part of the present invention.

In the figure, reference number 1 is one of the A/D converters connected to the terminal of the pass line 5 of the CPU 6, and the 2
It is configured to send data in batches.

A gate circuit 7 is provided between the pass line 5 and the CPU 6, and this gate circuit 7 opens the gate only when the CPU 6 is inputting data from the A/D converter 1.

A signal indicated by C3 becomes active when one of the A/D converters 1 connected ahead of this gate circuit 7 is selected.

Further, the signal ADD is an address signal that specifies one of the A/D converters 1, and is input to the tecoder 10 through the switching circuit 9 when the signal C3 is active. A read pulse is sent to the gate circuit 4 of the D converter 1.

When the CPU 5 is not inputting data from each A/D converter 1, when the DIS signal is given to the flip-flop 16, the flip-flop 16 is set and its output operates the oscillation circuit 11 through the AND circuit 17. .

The output of the oscillation circuit 11 is sent to the counter circuit 12, thereby incrementing the counter output.

The output of this counter circuit 12 becomes an address signal for selecting one of the plurality of A/D converters 1, and when the C3 signal is not active, that is, when the CPU 5 is not executing data input, the switching circuit 9 For example, the output of the A/D converter 1 is sent to the Tecoder 10 through the gate circuit 4a.
and send it out onto the pass line 5.

At this time, a pulse is sent from the pulse generating circuit 13 to the latch circuit 14 in synchronization with the step of the counter circuit 12, so that the data on the pass line 5 is latched by the latch circuit 14.

Next, when the counter circuit 12 increments, data is simultaneously sent from the gate circuit 4b to the pass line 5, and another latch circuit 15 is sent by the pulse output from the pulse generation circuit 13.
latches that data.

At this time, the flip-flop 16 is simultaneously reset by the output pulse of the pulse generating circuit 13, so that the counter circuit 12 stops advancing.

3a, 3b, and 3c are display sections of the display circuit 3 that display applied data, and are composed of data, numeric display elements, and the like.

When the above operations are completed, the output data of the counter circuit 12, that is, the channel number (address signal) of the A/D converter 1 is displayed on the display section 3a, and the A/D signal is displayed on the display sections 3b and 3c.
/D converter 1 output data is displayed.

Next, when the pIS signal is sent again, the next A/D converter performs the same operation and can display the channel number and its output data.

By manually applying pulses to the DIS signal or repeatedly applying pulses using a timer, each A/D converter can be sequentially scanned and data can be displayed.

According to the present invention, as explained above, by disconnecting the bus from the CPU when the CPU is not inputting data and transferring data for display, the circuit structure is relatively simple and independent of the operation of the CPU. You can get the data display function.

The present invention has been described above with respect to a good embodiment thereof.
It is merely an example, and the present invention is not limited to the embodiments described herein.
It goes without saying that various modifications and changes may be made without departing from the technical scope thereof.

For example, in this embodiment, the oscillation circuit 11 is used as an address signal generation circuit that generates an address signal for selecting one of the A/D converters 1 when the CPU 6 is not inputting data from the A/D converter 1. , a counter circuit 12, a flip-flop 16, and an AND circuit 17 (a counter is used to continuously generate and scan the channel number (address signal) of each A/D converter),
The output of the counter circuit 12 is connected to the switching circuit 9, but as an alternative, for example, a signal generation circuit that manually generates the address signal of the A/D converter corresponding to each push button by pressing the push button may be used. randomly select any A
It is also possible to configure the device so that the /D converter can be selected.

Furthermore, in that case, the output of the signal generation circuit is disconnected from the switching circuit 9, and an address for selecting one of the A/D converters 1 when the CPU 6 is inputting data from the A/D converters 1 is set. The signal ADD used as a signal may be input directly to the tecoder 10 (in other words, the switching circuit 9 is omitted), and a switching circuit may be provided to switch the output of the tecoder and the output of the signal generation circuit as necessary. .

[Brief explanation of the drawing]

1, 2, and 3 are system diagrams showing an example of a conventional data display circuit, FIG. 4 is a system diagram showing an embodiment of a data display circuit according to the present invention, and FIG. 5 is a system diagram showing an example of a data display circuit according to the present invention. FIG. 2 is a block configuration diagram showing a detailed embodiment of the main part of a data display circuit. 1...A/D converter, 2...
...Digital signal line, 3...Display circuit, 3a, 3b, 3c...Data display section, 4.4a, 4b...・CPU data input gate circuit, 5....-CPU data bus, 6....CPU (central processing unit), 7.... Gate circuit for disconnecting the CPU bus, 8... Control circuit, 9...
...Address signal switching circuit, 10...
Address signal tecoder, 11...Oscillation circuit, 12...Counter circuit, 13...
...Pulse generation circuit, 14, 15...
...Display data latch circuit, 16...
・Flip-flop, 17...AND circuit.

Claims (1)

[Scope of utility model registration request] In a data acquisition circuit in which a CPU inputs and processes output data from a large number of A/D converters, etc., the CPU's data bus connected to a gate circuit provided on the output side of the A/D converters, etc. an address signal generation circuit that generates an address signal for selecting one of the A/D converters when no data is input from the A/D converter, etc.; and an address signal generation circuit provided at a connection point on the CPU side of the data bus. The CPU
a second gate circuit that closes the gate when the device is not inputting data from the A/D converter or the like; and an A/D converter connected to the input side of the second gate circuit and selected by the address signal. a latch circuit that latches data output from the device to the data bus; a pulse generation circuit that sends a pulse to the latch circuit in synchronization with the generation of the address signal; and a pulse generation circuit that displays the data latched by the latch circuit. A data display circuit comprising a display circuit.