JPS6032423A - Digital filter - Google Patents

Digital filter

Info

Publication number
JPS6032423A
JPS6032423A JP14101583A JP14101583A JPS6032423A JP S6032423 A JPS6032423 A JP S6032423A JP 14101583 A JP14101583 A JP 14101583A JP 14101583 A JP14101583 A JP 14101583A JP S6032423 A JPS6032423 A JP S6032423A
Authority
JP
Japan
Prior art keywords
value
circuit
delay
forecast
rounding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14101583A
Other languages
Japanese (ja)
Inventor
Masaaki Takizawa
正明 滝沢
Norihiko Fukinuki
吹抜 敬彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14101583A priority Critical patent/JPS6032423A/en
Publication of JPS6032423A publication Critical patent/JPS6032423A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00Networks using digital techniques
    • H03H17/02Frequency selective networks
    • H03H17/04Recursive filters
    • H03H17/0461Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE:To reduce the propagation of transmission error due to omission of fractions and rounding by rounding or discarding fractions produced by multiplication of filter coefficient, giving a delay to a value decided by quantizing error for a prescribed period and then adding the value to the next input signal. CONSTITUTION:A signal value X generated by a signal generator 1 is subject to subtraction with a forecast value (x) at a subtraction circuit 2 and a quantizer 3 applies quantization in response to the value (X-x) and allocates a code word. A representative is set (4) based thereupon, added (5) to the forecast value (x), forecast values M, N delayed through a 1-picture element delay circuit 6 and a 1-line delay circuit 7 are obtained and the values produce the forecast value (x) through an adder circuit 8 and a 1/2-multiple circuit 9. In this case, a fraction (m) discarded by the 1/2-multiple circuit 9 is subject to 1-picture element delay by a delay circuit 10, the value is doubled into 2m by a double circuit 11, the value is added to the output (M+N) of the circuit 8 and the forecast value is obtained.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は再帰型ディジタルフィルタ、特に帰還係数が非
整数の時に生じる量子化誤差の伝播の防止に好適なディ
ジタルフィルタの構成に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a recursive digital filter, and particularly to a configuration of a digital filter suitable for preventing propagation of quantization errors that occur when the feedback coefficient is a non-integer.

〔発明の背景〕[Background of the invention]

画像等の2次元惰号を予測符′号化する方法として、第
1図(a)に例示する1次元符号化と(b)に示す2次
元符号化法とが知られる。即ち、1次元符号化は走:f
、線内の直前の画素(の組合せ)を用いて符号化すべき
画素を予測し、それと実際の値との差分(予測誤差)を
符号化する。2次元符号化は、直前の走査線の画素をも
用いて予測し、予測誤差を符号化する。
As a method for predictively encoding a two-dimensional code such as an image, there are known a one-dimensional encoding method illustrated in FIG. 1(a) and a two-dimensional encoding method illustrated in FIG. 1(b). That is, one-dimensional encoding is run: f
, the pixel to be encoded is predicted using (a combination of) the immediately preceding pixels in the line, and the difference (prediction error) between it and the actual value is encoded. Two-dimensional encoding also uses pixels of the immediately preceding scanning line to make predictions and encodes prediction errors.

これらの予測に用いる画素配置の違いにより、両符号化
は以下の特徴を持つ。即ち、1次元符号化は走査線内の
画素のみを用いて予測を行なうので、一般に予測誤差が
大きい。しかし、伝送誤まりが生じた時は、その影響が
走を線内に限定されるので、これによる画質劣化は小さ
い。2次元符号化は、これとは逆に予測誤差1ケ小さい
が、伝送誤まりが生じた時に、走査線間に影響が伝播す
るため、これによる画質劣化は大きい。
Due to the difference in pixel arrangement used for these predictions, both encodings have the following characteristics. That is, since one-dimensional encoding performs prediction using only pixels within a scanning line, prediction errors are generally large. However, when a transmission error occurs, its influence is limited to within the line, so the deterioration in image quality due to this is small. On the contrary, in two-dimensional encoding, the prediction error is one order of magnitude smaller, but when a transmission error occurs, the influence propagates between scanning lines, resulting in a large deterioration in image quality.

ζて、伝送誤りの影響は、μmトの2棹類に大別できる
。第1は、これらの予測符号化やそれの復号化を行なう
予測符号器、4号器の計n梢度が無限に大きいとし7ヒ
場合にも生じるものである。この影響を防止することは
不可能であり、また、伝播する距離に応じていくらでも
影響は小さくなる。
Therefore, the effects of transmission errors can be roughly divided into two categories: μm and μm. The first problem occurs even when the total number of the predictive encoders and four coders that perform predictive encoding and decoding is infinitely large. It is impossible to prevent this effect, and the effect becomes smaller depending on the distance of propagation.

第2は、上記の計算IT/I Ifが有限なことにより
生じるものである。即ち、これが有限なために、予測値
は切捨て、又は、丸め等が行なわれるが、伝送誤まりの
ため符号器・復号器間で予測に用いる1画素の信号値が
異なるので、切捨てや丸めの結果が異なることがある。
The second reason is that the above calculation IT/I If is finite. In other words, since this is finite, the predicted value is truncated or rounded, but because the signal value of one pixel used for prediction differs between the encoder and decoder due to transmission errors, truncation or rounding is not necessary. Results may vary.

これらの結果が異なることによる伝送誤まりの伝播は、
原理的に無限に連続する。以上は、画(象の予測符号化
回路について述べたが、上記符号化回路は一棟の再帰型
ディジタルフィルタを構成し、一般の再帰型ディジタル
フィルタにおいても演算処理における「まるめ」による
誤りが発生する。
The propagation of transmission errors due to these different results is
In principle, it continues indefinitely. The above describes a picture-like predictive coding circuit, but the above coding circuit constitutes a recursive digital filter, and errors due to "rounding" occur in arithmetic processing even in general recursive digital filters. do.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、再帰型ディジタルフィルタの有限の計
E)i 14度において、上記の切捨てや丸めによる伝
送誤まりの伝播を軽減する手段を実現することにある。
An object of the present invention is to realize a means for reducing the propagation of transmission errors due to the above-mentioned truncation and rounding in the finite total E)i of 14 degrees of a recursive digital filter.

〔発明の概要〕 上記目的を達成するため、本発明はフィルタの出力信号
に系敬を乗じ、入力信号に加える再帰型ディジタルフィ
ルタにおいて、上記係数を乗することによる端数を四捨
五入、又は切捨てによる量子化誤差から定まる値を一定
期間遅延した後に次の入力信号に加算することを特徴と
する。
[Summary of the Invention] In order to achieve the above object, the present invention provides a recursive digital filter in which the output signal of the filter is multiplied by a coefficient and added to the input signal. It is characterized by adding the value determined from the conversion error to the next input signal after delaying it for a certain period of time.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の効果を図により説明する。即ち、第1図
(b)に示す画素M、Nとを用いて、画素Xの予測値X
を式(1)で予測する場合を例にして説明する。
Hereinafter, the effects of the present invention will be explained using figures. That is, using the pixels M and N shown in FIG. 1(b), the predicted value X of the pixel
An example will be explained in which the prediction is made using equation (1).

ただし、X、M、Nは整数、〔〕は整数への切捨て、m
は@前の画素Mにおいて切捨てられた端数を表わす。
However, X, M, N are integers, [ ] is rounded down to an integer, m
@represents the rounded down fraction at the previous pixel M.

ここで、元の信号が全て0の時に、伝送誤りにより、丸
で囲んだ画素が+5と誤まってしまった場合の伝送誤り
の伝播の様子を第2図に例示する。
FIG. 2 shows an example of how the transmission error propagates when the circled pixel is mistaken as +5 due to a transmission error when all original signals are 0.

ただし、()内はそのl[!11素において切捨てられ
た端数を示す。
However, the information in parentheses is the l[! Shows the rounded down fraction in 11 elements.

比較のため、式(2)のように従来の四捨五入により丸
めた場合 の伝送誤りの伝播の様子を第3図に併せ示す。なお、丸
めの代りに切捨てを行なう場合には、上記の+5を−5
に置換すると、第3図と同様の結果になる。
For comparison, FIG. 3 also shows how transmission errors propagate when rounding is performed using conventional rounding as in equation (2). If you want to truncate instead of rounding, change the above +5 to -5.
, a result similar to that shown in FIG. 3 is obtained.

第2図、第3図を比較すると、前者は有限の範囲で元の
信号(全0)に収束するが、後者は収束せず、むしろ範
囲が拡大していくことがわかる。
Comparing FIG. 2 and FIG. 3, it can be seen that the former converges to the original signal (all 0s) within a finite range, but the latter does not converge, and rather the range expands.

次に上記実施例を具体化するための符号器のブロック図
を第4図に示す。図において、点線内が本発明の%徴で
あり、残りの部分は、例えば[画像のディジタル信号処
理」、日刊工業新聞社刊、P147.図963等に詳し
い。
Next, a block diagram of an encoder for embodying the above embodiment is shown in FIG. In the figure, the percentages of the present invention are shown within the dotted lines, and the remaining parts are shown in, for example, [Digital Signal Processing of Images], published by Nikkan Kogyo Shimbun, P147. See Figure 963 for details.

信号発生器(例えばA/D変換器)1で発生した信号値
Xは、引算回路2により予測値Xとの差をとられる。量
子化器3は、上記の(X−XlのjilIK応じて量子
化を行ない符号@を割当てる。この符号語に基づいて、
代表値設定回路4は代表値を設定し、上記の予測値Xと
の和を加算器5によりとる。その加算結果は、1画素遅
延回路6.1ライン遅延回路7を通して遅延され予測値
M、Nとなる。この値M、Nは加算回路8.1/2倍回
路9を通して予測値Xを生成する。
A signal value X generated by a signal generator (for example, an A/D converter) 1 is subtracted from a predicted value X by a subtraction circuit 2 . The quantizer 3 performs quantization according to the jilIK of (X-Xl) and assigns the code @. Based on this code word,
The representative value setting circuit 4 sets a representative value, and the adder 5 calculates the sum with the predicted value X described above. The addition result is delayed through a 1-pixel delay circuit 6 and a 1-line delay circuit 7 to become predicted values M and N. These values M and N are passed through an adder circuit 8 and a 1/2 times circuit 9 to generate a predicted value X.

次に本発明の特徴である点線内を説明する。まず、上記
の172倍回路で切捨てられた端数mは、遅延回路10
により1画素遅延され、さらに2倍回路11によりその
値は2倍され2mとなる。この値は、加算回路12によ
り、加算回路8の出力(M+N )と加算され、式(1
)を得る。
Next, the features of the present invention within the dotted lines will be explained. First, the fraction m rounded down in the above 172x circuit is the delay circuit 10
is delayed by one pixel, and the value is further doubled by the doubling circuit 11 to become 2m. This value is added to the output (M+N) of the adder circuit 8 by the adder circuit 12, and the value is added to the output (M+N) of the adder circuit 8 using the formula (1
).

復号器の構成を第5図に示す。第4図と同一の番号のブ
ロックが同一の機能を持つ。特に本発明の範囲内は、第
4,5図共通なので説明は省略する。
The configuration of the decoder is shown in FIG. Blocks with the same numbers as in FIG. 4 have the same functions. Particularly, since the scope of the present invention is common to FIGS. 4 and 5, explanation thereof will be omitted.

なお、以下も本発明の範囲内であることは明白である。It is clear that the following also falls within the scope of the present invention.

(1) 上記実施例においては、第1図(b)に示す予
測係数を採用したが、他の任意の予測係数または予測画
素を用いてもよい。−例として、第1図(a)に示す1
次元符号化に本発明を適用した場合と、従来の四捨五入
による場合とを第6.第7図に示の方法では、予測曲が
0に収束しないが、本発明では0に収束していることが
わかる。
(1) In the above embodiment, the prediction coefficients shown in FIG. 1(b) are used, but any other prediction coefficients or prediction pixels may be used. - As an example, 1 shown in Figure 1(a)
The case where the present invention is applied to dimension coding and the case using conventional rounding are explained in Section 6. It can be seen that the predicted music does not converge to 0 with the method shown in FIG. 7, but converges to 0 with the present invention.

(2)遅延回路10は、1画素に限ることはなく、例え
ば走食線方向の予411]値を遅延させる遅延回路6と
同じ画半数だけ遅延してもよい。むろん遅延回路10の
かわりに、遅延回路6に入力する信号に上記の端数を加
算しても効果は全く同じである。
(2) The delay circuit 10 is not limited to one pixel; for example, the delay circuit 10 may be delayed by half a pixel, which is the same as the delay circuit 6 which delays the pre-411] value in the direction of the scanning line. Of course, the effect is exactly the same even if the above fraction is added to the signal input to the delay circuit 6 instead of the delay circuit 10.

(3)上記の端数mは、走査線毎、又はフィール゛ ド
初など、あらかじめ定められた周期毎に0等にリセット
してもよい。
(3) The above fraction m may be reset to 0 or the like at every predetermined period, such as every scanning line or the beginning of a field.

(4)伝送誤1りの伝播をさらに減少させるために、1
フイールド毎、又は、フレーム毎に直上の走査線を仮旬
的に全白や全黒とみなして符号化・復号化してもよい。
(4) In order to further reduce the propagation of transmission error 1,
Encoding and decoding may be performed by temporarily treating the scanning line immediately above as completely white or completely black for each field or frame.

この場合、符号器、復号器間の同期をとるため、特別の
制御調号を伝送しても良い。
In this case, a special control key code may be transmitted in order to synchronize the encoder and decoder.

(5)以上は、画像信号を対象に説明したが、任意の信
号に対して、同様に考えられる。また、入力毎号と予測
値の差を予測符号化した例を説明したが、一般のディジ
タルフィルタでは、この予測符号化は不要であることは
当然である。
(5) The above description has been made with reference to image signals, but any signal can be similarly considered. Further, an example has been described in which the difference between each input signal and the predicted value is predictively encoded, but it goes without saying that this predictive encoding is not necessary in a general digital filter.

(6)上記の説明では、端数をそのtま帰還させたが、
これから定まる値(例えば172倍した値等)、を帰還
させてもよい。
(6) In the above explanation, the fraction was returned to that number, but
A value determined from this (for example, a value multiplied by 172) may be fed back.

〔発明の効果〕〔Effect of the invention〕

以上説、明したように、1次元符号化においては、同じ
桁数で計算しても本発明においては予測値が0に収束し
、従来の方法では収束しない。さらに42次元符号化で
は、1走査線の遅殆が必要であるが、本発明では、端数
を切捨てた結果のみを遅延すればよいので、多数の桁数
を要する従来の方法よりもハードウェア規模も小さくで
きる。従って、実用上効果が大きい。
As explained above, in one-dimensional encoding, even if calculations are made using the same number of digits, the predicted value converges to 0 in the present invention, whereas it does not converge in the conventional method. Furthermore, in 42-dimensional encoding, a delay of one scanning line is required, but in the present invention, only the result of truncating fractions needs to be delayed. can also be made smaller. Therefore, it has a great practical effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1次元符号化と2次元祠号化の説明図、第2.
第6図ならび第3.第7図は各々本発明と従来の方法に
おける伝送誤り伝播を説明する図、第4および第5図は
それぞれ本発明の一実施例を説明する2次元符号器およ
びゆ号器のブロック図である。 1・・・信号発生器、2・・・引算回路、3・・・量子
化器、4・・・代表値設定回路、5,8.12・・・加
尊回路、6.10・・・遅延(1画素)回路、7・・・
遅延(1走¥i1図 000 θ θ 0 θ Oθ θ −(0)(0)(
0)(0ン(θン(0)(0)(θ)(θ)<0)−θ
 θ 0 ρ■Z/I θq−−− (θ) (θ) (0ン(ρン(θ)(−E)(+2(
θ)(J「)(アラθ θ ozzzrrao− (0)(θ) (の(刊1)(+ン(θ〕(t) (0
) (づテン(責)θ θ l l Z I I I 
Q σ −−−(0) (Oン (の(+ン(0) (
+2cすン(0)(責ン(す〕晶糟0晶j席2.(、晶
:)<’!+ ’−σ ρ l l l l θ θ 
θ θ(0)(+Hの(θ〕(θ)(ρ)(+)(t)
(う)(責)−−θ θ l l l θ θ θ θ
 θ −一−(0)(す) (0) (1)ノ(0)(
す)(+)(づ1)(ナノ<4)Oθ 11 ρ ρ 
θ ρ ρ ′−−−(0λ(4:〕(θ)(θ)(f
)(廻t−kH女)(−1バナノθ 000 θ ρ 
ρ t ρ ρ (0ン (看H−k)<−k)(÷)(士](+1(±
)(幻 (責〕 −−−θ θ θ θ ρ ρ ρ 
ρ θ ρ −−−(11)(0)(θJ(1)ン(θ
ン(tz)(0ン(Q)(θ)(θ2θ θ 0 ρ 
θ θ 0 θ 00−0000■3 Z I I +
 − θ θ θ 3332222−− 00 Z333 3 333−− 0 1 233 33333−−− 1 2333 33 333−−− 不 4 図
Figure 1 is an explanatory diagram of one-dimensional encoding and two-dimensional encoding, and Figure 2.
Figure 6 and Figure 3. FIG. 7 is a diagram explaining transmission error propagation in the present invention and the conventional method, respectively, and FIGS. 4 and 5 are block diagrams of a two-dimensional encoder and a decoder, respectively, explaining an embodiment of the present invention. . DESCRIPTION OF SYMBOLS 1... Signal generator, 2... Subtraction circuit, 3... Quantizer, 4... Representative value setting circuit, 5, 8.12... Calculation circuit, 6.10...・Delay (1 pixel) circuit, 7...
Delay (1 run ¥i1 figure 000 θ θ 0 θ Oθ θ −(0)(0)(
0)(0n(θn(0)(0)(θ)(θ)<0)-θ
θ 0 ρ■Z/I θq−−− (θ) (θ) (0n(ρn(θ)(-E)(+2(
θ) (J") (ara θ θ ozzzzrrao- (0) (θ)
) (Zuten (responsibility) θ θ l l Z I I I
Q σ −−−(0) (Oon (of(+n(0) (
+2c sun (0) (responsibility (su) crystal 0 crystal j seat 2. (, crystal:) <'!+ '-σ ρ l l l l θ θ
θ θ (0) (+H's (θ) (θ) (ρ) (+) (t)
(U) (Responsibility) --θ θ l l l θ θ θ θ
θ −1−(0)(su) (0) (1)ノ(0)(
) (+) (zu1) (nano<4)Oθ 11 ρ ρ
θ ρ ρ ′−−−(0λ(4:)(θ)(θ)(f
) (Mawari t-kH woman) (-1 Banano θ 000 θ ρ
ρ t ρ ρ (0n (seeH-k)<-k) (÷) (shi] (+1 (±
) (illusion (responsibility) −−−θ θ θ θ ρ ρ ρ
ρ θ ρ ---(11)(0)(θJ(1)n(θ
(tz) (0 (Q) (θ) (θ2θ θ 0 ρ
θ θ 0 θ 00-0000■3 Z I I +
- θ θ θ 3332222-- 00 Z333 3 333-- 0 1 233 33333-- 1 2333 33 333-- No 4 Figure

Claims (1)

【特許請求の範囲】[Claims] 1、 フィルタの出力信号に非整数の係数を乗じ、再帰
的に入力信号と加え合せる再帰型ディジタルフィルタに
おいて、上記の非整数倍することにより生ずる端数を四
捨五入、又は、切捨てたことによる量子化誤差から定ま
る値を、一定期間遅延した後に、次の入力信号に加曽:
することを特徴とするディジタルフィルタ。
1. In a recursive digital filter that multiplies the output signal of the filter by a non-integer coefficient and recursively adds it to the input signal, quantization error due to rounding or truncating the fraction caused by multiplying by the above non-integer After a certain period of delay, apply the value determined from to the next input signal:
A digital filter characterized by:
JP14101583A 1983-08-03 1983-08-03 Digital filter Pending JPS6032423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14101583A JPS6032423A (en) 1983-08-03 1983-08-03 Digital filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14101583A JPS6032423A (en) 1983-08-03 1983-08-03 Digital filter

Publications (1)

Publication Number Publication Date
JPS6032423A true JPS6032423A (en) 1985-02-19

Family

ID=15282207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14101583A Pending JPS6032423A (en) 1983-08-03 1983-08-03 Digital filter

Country Status (1)

Country Link
JP (1) JPS6032423A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60261210A (en) * 1984-06-08 1985-12-24 Sony Corp Digital filter circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60261210A (en) * 1984-06-08 1985-12-24 Sony Corp Digital filter circuit
JPH0622315B2 (en) * 1984-06-08 1994-03-23 ソニー株式会社 Digital filter circuit

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