JPS60263510A - Frequency multiplying circuit - Google Patents

Abstract

PURPOSE:To reduce the number of required circuits other than a microcomputer to obtain a doubled signal by interrupting the microcomputer through an exclusive OR gate to process a square wave signal. CONSTITUTION:The speed signal from a speed sensor 4 is converted to a square wave speed signal by a waveform shaping circuit 5. This square wave speed signal is supplied to one input terminal 3a of an exclusive OR gate 1, and the other input terminal is connected to an output port 3b of a microcomputer 2. The output terminal of the gate 1 is connected to an interrupt input terminal 3c of the microcomputer 2. The speed signal is doubled by actions of the gate 1 and the microcomputer 2. Thus, the input signal is doubled in the circuit constitution where only exclusive OR gate is provided as required circuits other than the microcomputer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency multiplier circuit that doubles the frequency of an input signal.

[Prior art]

Conventionally, this type of frequency multiplier circuit is composed of a phase-ron loop, and requires a reference oscillation circuit, a phase detection circuit, a frequency division circuit, and the like. Then, the microcomputer has 2
Even when inputting a multiplied signal, the above-mentioned circuit is required, which increases the number of circuit elements required outside the microcomputer, which causes the problem that the overall circuit configuration becomes complicated. be.

[Problem that the invention seeks to solve]

The present invention reduces the number of circuits required outside the microcomputer and obtains a doubled signal.

[Means for solving problems]

In order to solve the above problems, the present invention includes a signal generating means for generating a frequency signal whose signal level repeatedly changes between "H' and "L", and a frequency signal from this signal generating means is connected to one input terminal. an exclusive OR gate received at the input terminal, and an output signal of this exclusive OR gate received at the input terminal,
When the output signal is an inversion processing request signal, an inversion processing operation is executed and the exclusive OR gate is sent from the output terminal to the other input terminal of the exclusive OR gate at the next signal level change of the input signal. and a microcomputer that applies a signal necessary to convert the output signal of the gate into an inversion processing request signal, so that the exclusive OR gate generates an output signal with twice the frequency of the input signal. It is a feature.

〔Example〕

The present invention will be described below with reference to embodiments shown in the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In Fig. 1, numeral 4 is a speed sensor that is attached to the speedometer cable shaft of the vehicle and generates a frequency signal proportional to the running speed of the vehicle, and 5 is a frequency signal generated by the speed sensor 4 (hereinafter referred to as the speed signal). ) in Figure 2 (
In the waveform shaping circuit shown in 1), 1 is an exclusive OR gate, and 2 is a microcomputer (hereinafter referred to as microcomputer). A speed signal is input to one input terminal 3a of the exclusive OR gate 1, and the other input terminal is connected to an output port 3b of the microcomputer 2. Further, the output terminal of the exclusive OR gate 1 is connected to the interrupt input terminal 3c of the microcomputer 2, and the speed signal is doubled by the action of the exclusive OR gate 1 and the microcomputer 2.

The microcomputer 2 integrates the doubled speed signal for a certain period of time, calculates the running speed of the vehicle from the integrated value, converts the calculation result into display data, and then outputs it to the display drive circuit 6.

The display drive circuit 6 drives the display segment of the display element 7 corresponding to the display data based on the display data output from the man-con 2 to display the speed.

Its operation will be explained in a steam configuration.

The speed signal shown in FIG. 2 (1) is input to the input terminal of the exclusive OR gate 1, and the time in FIG.
”, the microcontroller 2 connected to the other input terminal
Since the output port 3b of is "H", the output of the exclusive OR gate 1 goes from "H" to "L", and the microcomputer 2 changes the interrupt input terminal 3c from "L" level or from "H" to "L". The transition to is detected, normal processing is interrupted, and the interrupt processing shown in FIG. 3 is executed.

In this interrupt processing, the speed counter is integrated for speed calculation, and other speeds and distances (
- For example, after performing arithmetic processing (the time required to execute this processing is shown in the second FI! JTO) regarding the integration of the distance counter for the mileage hand, the inversion processing of the output level of the output port 3b is performed. Execute, terminate interrupt processing, and resume suspended normal processing. This normal process is
As shown in Figure 4, every time a predetermined time elapses (the preset speed gate timer is decremented by the internal timer and becomes 0), the vehicle running speed is calculated from the value of the speed counter accumulated in the interrupt processing, and Perform processing to display the .

As a result of the inversion process of the output port 3b executed by the decoupling microcomputer 2, the output port 3b transitions from "H" to "L" at time t2 as shown in FIG. 2 (2), and the exclusive OR gate 1 The output ((3) in FIG. 2) transitions from "L" to "H" and cancels the interrupt request to the microcomputer 2.

Hereinafter, at t3 in FIG. 2, when the speed signal changes from "H" to "L", the signal to the interrupt input terminal 3C of the microcomputer 2 goes from "H" to "L" level and interrupt processing is executed again.

Thereafter, the above sequence is repeated from t5+L5 onward in FIG. 2, so that the period T of the speed signal shown in FIG.
An interrupt request to the microcomputer 2 is made at a cycle T/2, which is 1/2 of the period T/2.

As is clear from the above explanation, the speed signal is multiplied by two and input to the microcomputer 2. By multiplying the speed signal and inputting it to microcomputer 2, microcomputer 2
This has the great effect of doubling the calculation accuracy of speed display calculations.

Although the above embodiment has been described using a vehicle speed signal as an input signal, any other type of frequency signal can also be used, and an example of this is an engine rotation signal.

〔Effect of the invention〕

As described above, according to the present invention, there is an excellent effect that an input signal can be multiplied by 02 with a small circuit configuration that requires only an exclusive OR gate outside the microcomputer.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation, and FIGS. 3 and 4 are calculation flow charts showing the calculation processing of the microcomputer. 1... Exclusive OR circuit, 2... Microcomputer, 4... Speed sensor. Representative Patent Attorney Takashi Okabe Figure 1 Figure 2 = Nagi-: : t+ t2t3t4ts Sat- 4th

Claims (1)

[Claims] a signal generating means for generating a frequency signal whose signal level repeatedly changes between "H" and "L"; an exclusive OR gate receiving the frequency signal from the signal generating means at one input terminal; An output signal of the exclusive OR gate is received at an input terminal, and when the output signal is an inversion processing request signal, an inversion processing operation is performed and the output signal is transferred from the output terminal to the other input terminal of the exclusive OR gate. a microcomputer that applies a signal necessary to turn the output signal of the exclusive OR gate into an inversion processing request signal at the next signal level change of the input signal; A frequency multiplier circuit that generates an output signal with twice the frequency.