JPS60251296A - Method for plating fine pattern - Google Patents

Method for plating fine pattern

Info

Publication number
JPS60251296A
JPS60251296A JP10654784A JP10654784A JPS60251296A JP S60251296 A JPS60251296 A JP S60251296A JP 10654784 A JP10654784 A JP 10654784A JP 10654784 A JP10654784 A JP 10654784A JP S60251296 A JPS60251296 A JP S60251296A
Authority
JP
Japan
Prior art keywords
plating
pattern
cathode
air blowing
anode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10654784A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Mayumi
真弓 喜行
Ryohei Koyama
亮平 小山
Kaoru Omura
馨 大村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Corp
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Asahi Kasei Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd, Asahi Kasei Kogyo KK filed Critical Asahi Chemical Industry Co Ltd
Priority to JP10654784A priority Critical patent/JPS60251296A/en
Publication of JPS60251296A publication Critical patent/JPS60251296A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/241Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus

Landscapes

  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To manufacture a printed circuit having a finer pattern by stirring a plating soln. by air blowing and cathode rocking so as to prevent the formation of a circular unplated part and burning. CONSTITUTION:When a fine pattern is formed on a substrate for a precision printed circuit by plating, a plating soln. is stirred by cathode rocking at >=1.0m/ min linear velocity in a direction parallel to an anode and air blowing at >=0.01m<3>/min flow rate per unit area (m<2>) of the bath. Thus, the formation of an unplated part probably due to bubbles or gaseous H2 on a fine circuit pattern in case of only air blowing is prevented, and burining due to reduced limiting current density in case of only cathode rocking is also prevented.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、精密印刷回路基板などに施す微細パターンメ
ッキ法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a fine pattern plating method applied to precision printed circuit boards and the like.

〈従来の技術〉 従来から精密な印刷回路基板を作る場合フォトリソグラ
フィがよく用いられてきたが、特にアディティブ法を用
いることによって高配線密度の回路基板ができ、かなり
有利な製造法であるとされてきている。ところで、回路
基板の配線密度は近年増々高密度化の方向にあシ、更に
微細な回路パターンをメッキによって形成させようとす
る場合、メッキ液の攪拌方法には、一般に空気攪拌ある
いはカソードロッキング(陰極板を揺動することが)が
行なわれている。
<Conventional technology> Photolithography has traditionally been frequently used to produce precision printed circuit boards, but the use of additive methods in particular allows circuit boards with high wiring density to be produced, and is considered to be a highly advantageous manufacturing method. It's coming. Incidentally, the wiring density of circuit boards has been increasing in recent years, and when attempting to form even finer circuit patterns by plating, the plating solution is generally stirred using air agitation or cathode locking. rocking the board) is performed.

〈問題点〉 しかし、空気攪拌だけでは、原因はよくわからないが、
微細回路パターン上に気泡あるいは水素ガスによるもの
と思われる円形状のメツキネ着部が若干発生し、導体が
局部的に細くなって回路基板の信頼性が低下したり、あ
るいは程度のひどいものは導体パターンが断線してしま
う。また、一般に行われている様に、回路基板を陽極に
対し垂直方向にカソードロッキングするだけでは、限界
電流密度が下がりヤケが生じやすくなってしまう。そこ
で本発明者らは、空気攪拌とカソードロッキングを併用
することによって上記問題点を解決すべく鋭意検討を重
ねた結果本発明にいたった。
<Problem> However, the cause cannot be clearly understood with air agitation alone.
A small amount of circular bonding, which is thought to be caused by air bubbles or hydrogen gas, may occur on the fine circuit pattern, causing the conductor to become thin locally, reducing the reliability of the circuit board, or in severe cases, causing the conductor to become thinner. The pattern is broken. Further, if the circuit board is simply cathode-locked in a direction perpendicular to the anode, as is generally done, the limiting current density will decrease and discoloration will easily occur. Therefore, the present inventors conducted intensive studies to solve the above problems by using air agitation and cathode locking in combination, and as a result, they arrived at the present invention.

〈構 成〉 すなわち、本発明は、陽極に対して平行方向に1.0 
g/jlb以上の線速度を有するカソードロッキングと
単位浴液面尚りの空気流量0.0I n1″/−i−/
r&以上の空気攪拌とを併用してメッキを行なうことを
特徴とするメッキ法を提供するものである。
<Configuration> That is, in the present invention, the angle of 1.0 in the direction parallel to the anode is
Cathode locking with a linear velocity of more than g/jlb and an air flow rate of 0.0I n1″/-i-/ at the unit bath liquid level
The present invention provides a plating method characterized in that plating is performed in combination with air agitation of r& or higher.

以下、本発明の詳細な説明する。The present invention will be explained in detail below.

本発明で行なう空気攪拌及びカソードロッキングは通常
の装置を使用すれば良いが、カソードロッキングの方向
は陽極に対して水平とする。その理由として陽極に対し
て垂直方向ではパターン上に付着した気泡あるいは水素
ガスを取り除き、なおかつ基板に損傷を与えない様な純
速度を得ることが難しいためである。空気攪拌と陽極に
対して水平方向のカソードロッキングを併用することに
よって、空気攪拌だけでは取り除けない微細回路パター
ン上の気泡あるいは水素ガスによると思われるメツキネ
着部の発生を防ぎ、カソードロッキングだけでは限界電
流密度が下がってヤケが生じやすくなるのを限界電流密
度を上げて光沢範囲の広い良好なメッキを得ることを可
能にしたものである。空気攪拌量はo、olrl/wi
g/r1以上が好ましく、特に0.03〜0.50−/
m/ゴ、更には0.05〜0650♂/−/♂が好まし
い。
Air agitation and cathode locking performed in the present invention may be performed using conventional equipment, but the direction of cathode locking is horizontal to the anode. The reason for this is that in the direction perpendicular to the anode, it is difficult to remove bubbles or hydrogen gas adhering to the pattern and to obtain a pure velocity that does not damage the substrate. By using both air agitation and cathode locking in the horizontal direction to the anode, it is possible to prevent the occurrence of air bubbles on the fine circuit pattern that cannot be removed by air agitation alone, or the occurrence of stuck spots that are thought to be caused by hydrogen gas, and the cathode locking alone is not enough. This method makes it possible to obtain good plating with a wide gloss range by increasing the limiting current density, which tends to cause discoloration when the current density decreases. Air stirring amount is o, olrl/wi
g/r is preferably 1 or more, particularly 0.03 to 0.50-/
m/g, more preferably 0.05 to 0650♂/-/♂.

また、カソードロッキングは陽極に対して水平に線速度
にして1.01rL/IIk以上で揺動するのが好まし
く、特に3.0−15.0 m/lk、更には5.0 
#15.0@/1w1nが好ましい。カソードロッキン
グを1.OV−以下にすると、回路パターン上に気泡あ
るいは水素ガスによると思われる円形状のメツキネ着部
を完全に除去出来ない。また、空気流量が0.01m1
’/#!#/ml’以下では限界電流密度も下がってヤ
ケが生じやすくなる。
Further, cathode rocking is preferably performed horizontally with respect to the anode at a linear velocity of 1.01 rL/IIk or more, particularly 3.0-15.0 m/lk, more preferably 5.0 m/lk.
#15.0@/1w1n is preferable. Cathode locking 1. If it is less than OV-, it is impossible to completely remove the circular stuck portions on the circuit pattern that are thought to be caused by bubbles or hydrogen gas. In addition, the air flow rate is 0.01 m1
'/#! If it is less than #/ml', the critical current density also decreases, making it easy to cause discoloration.

ところで、空気流量が多過ぎると、回路基板を腕曲させ
たり、メッキ液が浴槽の外へ飛散するなどの不都合が生
じてくるため、通常はt、o d/h/rl以下とする
By the way, if the air flow rate is too large, problems such as bending of the circuit board and splashing of the plating solution outside the bathtub will occur, so it is usually set to t, o d/h/rl or less.

また、カソードロッキングの線速度が速スキるとカソー
ド治具から回路基板がはずれてしまうなどの問題が発生
し易いため、通常は20.OTn/−以下とする。
In addition, if the linear speed of cathode locking is too fast, problems such as the circuit board coming off from the cathode jig are likely to occur, so normally 20. OTn/- or less.

本発明に使用する回路基板は、通常用いられているもの
であれば何でも良く、例えば、絶縁性基3− 板に片面あるいは用途によって両面に金属薄板を貼り合
わせ、その上にフォトレジストを用いてレジストパター
ンを形成し、導体部以外の不要な部分をエツチング除去
してその後レジストを剥離したもので良い。また、金属
薄板上にレジストを回路部以外のところに形成し、本発
明の方法でメッキを行ない、次いで金属薄板を除去する
方法に使用しても良い。
The circuit board used in the present invention may be any commonly used circuit board. For example, a thin metal plate may be bonded to an insulating substrate on one side or both sides depending on the purpose, and a photoresist may be applied thereon. A resist pattern may be formed, unnecessary portions other than the conductor portions may be removed by etching, and then the resist may be peeled off. Alternatively, a resist may be formed on a thin metal plate in areas other than the circuit portion, plated using the method of the present invention, and then used in a method in which the thin metal plate is removed.

電解メッキの種類としては、通常のものはすべて使用出
来、導電性及び経済性の点から銅が好ましいが、銀、金
、ニッケル等なんでも良い。メッキ液の種類としては、
銀メッキならばシアン化銀浴、金メッキならば酸性、中
性アルカリ性浴、ニッケルメッキならば硫酸ニッケル浴
、スルフアミノ酸ニッケル浴等が使用できる。銅の電解
メッキとしては、シアン化銅メッキ、ピロリン酸銅メッ
キ、硫酸銅メッキ、ホウフッ化銅メッキなどがある。
As for the type of electrolytic plating, all usual types can be used, and copper is preferred from the viewpoint of conductivity and economy, but any other metal such as silver, gold, or nickel may be used. The types of plating solution are:
Silver cyanide baths can be used for silver plating, acidic or neutral alkaline baths can be used for gold plating, and nickel sulfate baths, sulfamino acid nickel baths, etc. can be used for nickel plating. Examples of copper electrolytic plating include copper cyanide plating, copper pyrophosphate plating, copper sulfate plating, and copper borofluoride plating.

陰極電流密度としては通常の条件で良いが、微細なパタ
ーンをメッキする場合3 A/d−以上、特に5 A/
d♂以上、更には8 A/d♂以上が好ましく、4− 陰極電流密度を大きくすると幅方向への太シが抑制され
る。陰極電流密度は高い程好ましく、パルスメッキなど
も好ましく用いられる。陰極電流密度の上限はやけによ
り決定される。
The cathode current density may be under normal conditions, but when plating fine patterns, 3 A/d- or higher, especially 5 A/d- or higher.
d♂ or more, more preferably 8 A/d♂ or more, and 4- When the cathode current density is increased, thickening in the width direction is suppressed. The higher the cathode current density, the better, and pulse plating is also preferably used. The upper limit of cathode current density is determined by burnout.

その他の電解メッキ条件は通常の条件で行えば良い。Other electrolytic plating conditions may be carried out under normal conditions.

以下、本発明を実施例及び比較例により詳細に説明する
Hereinafter, the present invention will be explained in detail with reference to Examples and Comparative Examples.

実施例1〜5 ポリイミドフィルムデュポン社製「カプトン」厚さ25
μmのものVC5μm厚銅箔をボスチック社製rXA−
564−4J フェノール樹脂系接着剤を使って接着す
る。次にイーストマンコグツク社製ネガ型レジスト「マ
イクロレジスト747−110 cat Jを乾燥後レ
ジスト厚が3〜5μmになる様に銅面に塗布し、プリベ
ーク後、回路パターンマスクを通して高圧水銀ランプで
露光し、イーストマンコダック社製現像液[マイクロレ
ジストデベロッパー」及ヒイーストマンコダック社製リ
ンス液「マイクロレジストリンス」で現像し、ポストベ
ークして回路パターン状にレジストを形成する。続いて
、塩化第2鉄50チ洛液により銅箔をエツチング除去し
、ナガセ化成社製「レジスト剥離剤J−100Jを使っ
てレジストを剥離する。この結果膜厚5μms m 1
00μm1配列ピッチ150μmの線状パターンが得ら
れた。次にバーショウ村田製ビロリン酸銅メッキ液を用
い、前記線状パターンを陰極として空気攪拌量Q、IQ
 m”/m汐、カソードロッカーを線速度7.5■−で
陽極に対して水平に可動し、電流密度5.o A/dn
rの条件下でメッキを行なった。
Examples 1 to 5 Polyimide film “Kapton” manufactured by DuPont, thickness 25
μm VC5μm thick copper foil manufactured by Bostic rXA-
564-4J Adhere using phenolic resin adhesive. Next, after drying, a negative resist "Microresist 747-110 cat J" manufactured by Eastman Co., Ltd. was applied to the copper surface so that the resist thickness became 3 to 5 μm. After prebaking, it was exposed to a high-pressure mercury lamp through a circuit pattern mask. The resist is then developed using a developer (Microresist Developer) manufactured by Eastman Kodak and a rinsing liquid (Microresist Rinse) manufactured by Eastman Kodak, followed by post-baking to form a resist in the form of a circuit pattern. Subsequently, the copper foil was etched away using a 50% solution of ferric chloride, and the resist was removed using "Resist Remover J-100J" manufactured by Nagase Kasei Co., Ltd. As a result, the film thickness was 5 μm s m 1.
A linear pattern with an array pitch of 150 μm was obtained. Next, using a birophosphate copper plating solution made by Barshaw Murata, the linear pattern was used as a cathode to create an air agitation amount Q, IQ.
m”/m tide, the cathode rocker was moved horizontally with respect to the anode at a linear velocity of 7.5 μm, and the current density was 5.o A/dn.
Plating was performed under conditions of r.

この結果侍られた銅線状パターンにはヤケあるいは円形
状のメツキネ着部は皆無であった。
As a result, there was no discoloration or circular bonded areas in the copper wire pattern.

更に、表−1の如く空気攪拌蓋及びカソードロッカーの
線速度を変更し、前記と同種の銅線状パターンに同一の
条件でメッキを行なった。得られたパターンのヤケある
いは円形状のメツキネ着部の発生の有無を調べた。その
結果を表−1に示す。
Furthermore, the linear speeds of the air stirring lid and cathode rocker were changed as shown in Table 1, and plating was performed on the same type of copper wire pattern as described above under the same conditions. The resulting pattern was examined for discoloration or for the occurrence of circular matte areas. The results are shown in Table-1.

比較例1〜2 ポリイミドフィルムデュポン社製「カプトン」厚さ25
μmのものに5μm厚銅箔をボスチック社製rXA−5
64−4Jフェノール樹脂系接着剤を使って接着する。
Comparative Examples 1-2 Polyimide film “Kapton” manufactured by DuPont, thickness 25
Add 5μm thick copper foil to the μm one using Bostik rXA-5.
Adhere using 64-4J phenolic resin adhesive.

次にイーストマンコグツク社製ネガ型レジスト[マイク
ロレジスト747−110 cst J を乾燥後レジ
スト厚が3〜5μmになる様に、銅面に塗布し、プリベ
ーク後、回路パターンマスクを通して高圧水銀ランプで
露光し、イーストマンコダック社製現像液「マイクロレ
ジストデベロッパー」及びイースマンコダック社製リン
ス液「マイクロレジストリンス」で現像し、ポストベー
クし−C回路パターン状にレジストを形成する。続いて
、塩化第2鉄50チ溶液により銅箔をエツチング除去し
、ナガセ化成社製「レジスト剥離剤J −100Jを用
してレジストを剥離する。この結果、膜厚5μm1幅1
00μm1配列ピッチ150μmの線状パターンが得ら
れた。次にバーショウ村田製ビロリン酸銅メッキ液を用
い、前記線状パターンを陰極として空気攪拌量0.00
5 d71s/♂、カソードロッカーを線速度7.57
71/mで陽極に対して水平に可動し、電流密度5.O
A/d♂の条件下でメッキを行なった。
Next, a negative resist manufactured by Eastman Co., Ltd. [Microresist 747-110 cst J] was applied to the copper surface so that the resist thickness after drying was 3 to 5 μm, and after prebaking, it was applied using a high-pressure mercury lamp through a circuit pattern mask. It is exposed to light, developed with Eastman Kodak's developing solution "Microresist Developer" and Eastman Kodak's rinsing solution "Microresist Rinse," and post-baked to form a resist in the form of a -C circuit pattern. Next, the copper foil is etched away using a 50% solution of ferric chloride, and the resist is removed using Nagase Kasei Co., Ltd.'s "Resist Remover J-100J".As a result, the film thickness is 5 μm, width is 1.
A linear pattern with an array pitch of 150 μm was obtained. Next, using a birophosphate copper plating solution made by Barshaw Murata, the linear pattern was used as a cathode and the amount of air agitation was 0.00.
5 d71s/♂, cathode rocker linear velocity 7.57
71/m horizontally with respect to the anode, and the current density is 5. O
Plating was performed under A/d♂ conditions.

この結果得られた銅線状パターンには円形状のメツキネ
着部はなかったが、ヤケが発生した0更には、表−2の
如く空気攪拌量及びカソードロッカーの線速度を変更し
、前記と同種の銅線状パターンに同一の条件でメッキを
行なった0得られたパターンのヤケあるいは円形状のメ
ツキネ着部の発生の有無を調べた。その結果を表−2に
示すO 衣−1 ※1;拡大鏡を用いて、パターンを目視により観察し、
円形状のメツキネ着部の有無を調べた。
Although the copper wire pattern obtained as a result did not have a circular bonded area, it did cause some discoloration.Furthermore, the amount of air agitation and the linear speed of the cathode rocker were changed as shown in Table 2, and the above-mentioned The same type of copper wire pattern was plated under the same conditions, and the resulting pattern was examined to see if there was any discoloration or circular bonded areas. The results are shown in Table 2. *1: Using a magnifying glass, visually observe the pattern.
The presence or absence of a circular mesh attachment area was examined.

※2;パターンを目視し、ヤケを調べた0弐 −2 ※12※2共に表−1に示した方法によって調べた。*2; Visually inspected the pattern and checked for discoloration 02-2 *12 *2 Both were investigated using the methods shown in Table 1.

〈効 果〉 本発明の方法によりメッキを行うことにより、円形状の
メツキネ着部及びヤケが生じず、その結果、より微細な
パターンの印刷回路を製造することができる。
<Effects> By performing plating according to the method of the present invention, circular bonded areas and discoloration do not occur, and as a result, printed circuits with finer patterns can be manufactured.

特許出願人 旭化成工業株式会社Patent applicant: Asahi Kasei Industries, Ltd.

Claims (1)

【特許請求の範囲】[Claims] 陽極に対して平行方向に1.0@/−以上の線速度を有
するカソードロッキングと単位浴液面当りの空気流量0
 、OX yd/m/r1以上の空気攪拌とを併用して
メッキを行なうことを特徴とする微細パターンメッキの
方法
Cathode locking with linear velocity of 1.0@/- or more in the direction parallel to the anode and air flow rate per unit bath liquid level of 0
, a method of fine pattern plating characterized by performing plating in combination with air agitation of OX yd/m/r1 or more.
JP10654784A 1984-05-28 1984-05-28 Method for plating fine pattern Pending JPS60251296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10654784A JPS60251296A (en) 1984-05-28 1984-05-28 Method for plating fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10654784A JPS60251296A (en) 1984-05-28 1984-05-28 Method for plating fine pattern

Publications (1)

Publication Number Publication Date
JPS60251296A true JPS60251296A (en) 1985-12-11

Family

ID=14436382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10654784A Pending JPS60251296A (en) 1984-05-28 1984-05-28 Method for plating fine pattern

Country Status (1)

Country Link
JP (1) JPS60251296A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007277676A (en) * 2006-04-11 2007-10-25 C Uyemura & Co Ltd Electroplating method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944942A (en) * 1972-09-05 1974-04-27
JPS5376932A (en) * 1976-12-21 1978-07-07 Suzuki Motor Co Plating method
JPS57120693A (en) * 1981-01-16 1982-07-27 Seiko Epson Corp Plating method of gold alloy
JPS57210989A (en) * 1981-02-10 1982-12-24 Hiroshige Sawa Electroplating method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944942A (en) * 1972-09-05 1974-04-27
JPS5376932A (en) * 1976-12-21 1978-07-07 Suzuki Motor Co Plating method
JPS57120693A (en) * 1981-01-16 1982-07-27 Seiko Epson Corp Plating method of gold alloy
JPS57210989A (en) * 1981-02-10 1982-12-24 Hiroshige Sawa Electroplating method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007277676A (en) * 2006-04-11 2007-10-25 C Uyemura & Co Ltd Electroplating method

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