JPS60246155A - Code converting method - Google Patents

Abstract

PURPOSE:To realize a code suitable for high-density recording with a simple circuit by applying 7/8 conversion to a high-order 7 bits of the 1st data word of 16 bits by two data works of 8 bits and applying 9/10 conversion to 9 bits by the 2nd data of 8 bits. CONSTITUTION:A code word transmitted from a ROM104 or 105 is fetched by a parallel/serial converter (P/S)108, converted into a bit string and transmitted to an exclusive OR109. On the other hand, an inverse control circuit 110 calculates a select code SC based on a DP and F of a code word transmitted from the ROM14 or 105, a value of an integration value DSV up to the final bit LB of a preceding code word stored in an inverse control circuit 110 and an output LB of a D flip-flop 111 storing the final bit of the preceding code word transmitted, transmits the result to an exclusive OR109 to decide whether the codo word is brought into a back pattern or not. Thus, the DSV is controlled for both the 7/8 and 9/10 conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a code conversion method for converting an M-bit data word into an N-bit channel code word, which is applied when transmitting and recording digital signals. .

Conventional configurations and their problems In general, the following four points are known as properties necessary for communication channel codes used when magnetically recording digital signals.

(1) If the maximum number of consecutive bits = ``'0'' or ``1'' continues for too long, it will be difficult to extract clock information and the self-clock function will not be obtained. , in order to avoid this, it is desirable that the above-mentioned size be small.

(2) Minimum number of consecutive bits d: Since the magnetic recording and reproducing system has the property of blocking high frequency components, 110I+ and °
A channel code in which ``1'' changes frequently is not appropriate. Therefore, it is preferable that d be a dog.

(3) Detection window width TW: This is a measure of the phase direction margin against time axis fluctuations such as jitter of the reproduced signal and peak shift due to waveform interference, and the larger the value, the better.

(4) When the communication channels are connected by a rotary transformer such as in a VTR and the DC component is blocked, it is desirable that the channel code is a DC-free code that does not contain any DC component.

By the way, conditions (1), (2) and (4) above and (3)
The conditions are contradictory. Because (1) (2
) and (4), a data word consisting of M bits must be code-converted into a channel code word of N bits larger than M, but TW is defined as the pit length of the data word being T. This is because TV is always smaller than T in this case because it is given by Tw-M/NT. Therefore, in a communication channel where it is desirable to use a DC-free code, the channel code to be used differs depending on which of the above (1), (2+), or (3) is emphasized. If you increase it, Tm1n will increase, but
TVs are getting smaller.

Conventionally, various DC-free codes have been developed from the above point of view, including 8/9 conversion codes (Japanese Patent Application Laid-Open No. 5-1-1).
is one of them. According to the above definition, the 8/9 conversion code is d==1. ni=14. M=:8, N=9 and T. -8
It is a DC-free code with the feature of /9T, and T(1
, but has the disadvantage that k is large.

Purpose of the Invention The purpose of the present invention is to provide a DC-free code that maintains d, T, 1''i, and 8/9 conversion code the same, but reduces ki to 7 by half, and that can be realized easily and with a small circuit scale. That's true.

Structure of the Invention In order to achieve the above object, the present invention performs 16/18 conversion with equal savings by combining a 7/8 converted DC free one code and a 9/10 converted DC free one code, and obtains T(1). '= 8
/9 T and =7 constitutes a DC free code.

Two DC free codes, 7/8 transform and 9/10 transform, are both obtained by a general method of constructing a DC free code when d==1.

Next, the conditions for a DC-free code and the compositional strength method of a DC-free code in the case of d=1 will be explained. 1. (1) Regarding the DC free code, (I): The value obtained by assigning mo1 and ``○○pa1 to "1'" in the codeword and adding it is calculated as the disparity of the codeword - ( From then on D
In a bit string obtained by connecting channel codewords, the integral value of +1 and -1 from the beginning of the bit string to an arbitrary bit is called DSv (digital sum variation/). DSv is +
If the code is always finite without divergence across oO (-(equity)), then the code (-jDc) becomes a free code.

Next, (n) Regarding the construction method of DC free codes, (II)
- Since the code word length is finite, the DP is also finite, so by using a code word having a DP of opposite polarity to the DSV, depending on the sign of the DSV, it is possible to suppress the nsv to a finite value. Further, in order to keep k at a predetermined value, code words are selected based on the following criteria.

(n-1): When X is an integer greater than or equal to 1 and less than or equal to 1,
II The number β of consecutive bits of 1′° on the left side of the N-bit code word starting at 11+ is less than or equal to 1, and the number of consecutive bits of “O” or “1′°” r L on the right side H (β bit) B (b bit) R (β bit) is 1
In the middle part B of -x or less, and b = N-1-β bits, L and B are such that consecutive "0's and 1's appear alternately in 1 bit and below -) -" and H
For all bits of CCO, II OI+ and “1°゛,”1
Select the back pattern CCO of CCo in which "" and °"o" are replaced.

Next, the correspondence between code words and data words selected in this way will be described.

Code words cco, c selected in (II-2) and (■-1)
Among the codewords in which l is less than or equal to X, for the codeword CWO where the disparity -DP=O,
One data word is associated with each word. Further, among CC0, the code word CW1 where p is less than or equal to X and DP)o is made bare with its back pattern CW1, and data words are associated with each pair.

(It-3): Of the code word CCO, the above l is X-1-
Codeword CW2 where DP=O in one or more codewords
is paired with its back pattern CN3, and each bear is associated with a data word.

Next, it will be shown that the correspondence between code words and data words shown in (n-1) to (II-3) above satisfies the k limit and the nsv limit. However, l, =11, r
= r1 and the first code word W1 and 4 = 12 , r
It is assumed that a second code word W2 of = +2 is connected. Note that the final bit of Wl will be referred to as LB below.

(al) When W2=CWO, just connect 1.

Since CWo has DP=O, ID5VI will not increase even if its -i- is connected. Since the maximum value of rl is -x and the maximum value of l of Cwo is X, the number of consecutive bits of 0's or '1' at the connection will never exceed k.

(a2) Since the maximum value of l for both CWl and CWl is X, the restriction is satisfied for the same reason as (al). Therefore, it is only necessary to prevent an increase of 1 nsv I. Therefore, for DSV up to the last bit of Wl, C
Since DPi of Wl is positive, the connection rule is determined as follows.

(&21) When DSvo is W2=CW1 (&22)
When DSvkuo! 2=CW1(a3) CW2i4
Since DP=O, ID5v1 does not increase.

Therefore, only the k limit matters. Therefore, we define the connection rule as follows.

(&31) When LB is +1”, W2=CW2(13・
2) When LB is "o", the overlap part of W2=CW2CW2 is It 11+, so it is clear that the k restriction is satisfied.

(If-1) to ('1J-3) and (al) shown above
(2L3>), a DC-free code limited to d=1 can be obtained.

Table 1 shows the connection rules of (&1) to (&3) above. In Table 1, DSV'hO Narage DV="o", D
If SV (o na +:), DV = “1”, if DP = 0, P
If 1 = "1', DP〉O, then P 1 = "O°゛.

P2="O", DP (If O, P1="o".

P2 is set to a value of "1", P1 is the negation of the logical sum of all bits representing DP, and P2 is the in-hit value of DP. It represents the value of the last bit of the code word sent out LBijl before.

Also, F, mark 1; 1" or 'O°" at the beginning of 5
When the number of consecutive bits is 4 or more, it is F-"1゛°, and when it is 3 or less, it is F-"°0゛, and the select code SC
is a value of °゛1' when the code word is made into a back pattern; and "O" when the code word is left as is. However, 11 X I
I marks represent irrelevant values.

When Table 1 is expressed using a logical formula, it becomes formula (1).

5C=F ・LB 10 P1 ・DV ■ P2---(1) No.
1 Table However, °"·pa represents logical product, -" represents negation, "10" represents logical sum, and "e" represents exclusive logical sum.

By the way, as is clear from the correspondence between the data words and the data words, when N with a code word of DP=O is an even number, it is better to have N without a code word of DP=O with an odd number. Compared to the above case, the ratio of the number of code words that can have one-to-one correspondence with data words among the code words CCO and CCO is large. Therefore, for example, if N is an odd number in the M/2 N conversion, T is constant and the code word length is 2.
N (an even number), so a 2 M/2 N-converted DC-free code can be realized with a smaller k than an M/N-converted DC-free code. As shown earlier, in 8/9 conversion, k is 14
However, in 16/18 conversion, k can be 13 or less. However, in 16/18 conversion, the memory capacity used for code conversion and inverse conversion becomes large (example).

For the above reasons, when N is an odd number, using a plurality of Ill-free codes with an even code word length, 2 M/2
If we realize an N-transform DC-free code and keep T equal, we can make k smaller than the M/N-transform DC-free code, and the code conversion, It becomes possible to reduce the memory capacity required for inverse conversion.

In the present invention, in order to realize a 16/18 converted DC-free one code, a 7/8 converted DC-free one code and a 9/10 converted DC-free one code are used.
Two types of DC, both of which have an even code word length
Free codes are used.

However, °·'' represents a logical product, par-'' represents a negation, "■" represents an exclusive OR, and "'0" represents a logical OR.

1(-6, N
=8, we obtain a 7/8 converted DC free code with 132 codewords as shown in Table 2, and similarly, k=
7. Applying N=10 results in a 9/1° transformed DC-free code with 644 codewords as shown in Table 3.

However, Table 2.

F in Table 3 is the same as F in Table 1.

Note that in both Tables 2 and 3, X=3, but d=
1. = e's 7/8 conversion DCi free code MX%3 cannot do this. d=1. -=7f 7/8 converted DC free code and d=1. A 9/10 converted DC free code with 7 = 7 can be obtained with x-3 or x = 4, but it is more advantageous for clock recovery if the probability of appearance of 7 consecutive 1'' and 0'' is smaller. Therefore, the codes in Tables 2 and 3 are used.

Table 2 Table 3 Next, the present invention will be specifically explained using an example.0 Explanation of the Example In this example, a 16 bit data word is divided into 7 bits and 9 bits, and 7/8 Conversion and 9/MO conversion are performed at the same time, and the 18 bits of the converted result are recorded at the recording rate/r.
(=% f d , fd: data rate).

FIG. 1 shows an embodiment of a code conversion circuit for carrying out the method of the present invention. Hereinafter, the present invention will be explained in detail using FIG. 1.

When digitally processing a normal video signal, the video signal is quantized to 8 bits. This quantized video signal is taken into the parallel-to-serial converter (P/5) 101 shown in FIG.・The bit string sent from the Kurareru serial converter 101 is sent to the serial-parallel converter (S
/P) 102, it is summarized into 16 binoto parallel data. These 16 bits consist of two words of an 8-bit video signal.

The 16 bits are taken into the D flip-flop 103, and the top 7 bits of the output are stored in the ROM (Read 0n).
It is applied to the address input terminal of ly Memory) 1o 4, and on the other hand, it is applied to the address input terminal of fiROM 105 of the lower 9 pins. That is, the two-word video signal is divided into the upper seven bits of the first word and the least significant bit of the first word plus the entire second word, which is the total nine bits.

In the ROM 104, 8 bits corresponding to the 7 binoto data words are stored in the ROM 104.
The ROM 106 sends out the 10-bit code word corresponding to the 9-bit data word, 3 bits indicating its data value, and 1 bit indicating the above-mentioned F, for a total of 12 bits. A total of 14 pits, including 3 bits representing the disparity and 1 bit representing the F, are transmitted.

Regarding 9/1o conversion, IDPl in Table 3
, <4 are used. In Table 2 all codewords are 1DP144, so DP=O, ±2.
Since it is ±4, DP can be expressed with 3 bits. That is, DP=O: "o o o".

DP=2: “001”, DP=-2: “111”
”.

DP=4:'″C)10”, DP Knee 4: “1
1o".

The switching control circuit 106 includes ROM104 and ROM105.
The switching control signal is directly connected to the chip select terminal of 86M104, and connected to the chip select terminal of 86M105 via an inverter 1071.

By doing this, the 7/8 converted code word and the 9/1
The zero-converted code words can be sent out alternately.

The code word sent from 1'10M 104 or ROM 105 is sent to parallel-serial converter (P/5) 108.
is taken in, converted to a bit string and exclusive ORed with 10
Sent to 9th.

On the other hand, the DP and F of the code word sent from the ROM 104 or 105, the DSV value up to the last bit of the previous code word held in the inversion control circuit 110, and the value of the DSV sent from the previous code word. D that holds the last bit of the codeword
Based on the output LB of the flip-flop 111, a select code SC is calculated by the inversion control circuit 110U. After this, the select code SC is sent to the exclusive OR 109,
Determine whether or not to make the code word a back pattern. By doing so, the DSv can be controlled for both 9/8 conversion and 9/10 conversion.

As described above, it can be seen that the present invention can be realized with an extremely simple circuit configuration.

Furthermore, although the code word of fiF-"1'° was used in the above embodiment, it is possible to make the characteristics of the code match the characteristics of the communication channel without using the code word of F-"1° and DP=O. In this case, the codewords F − “1” and DP-0 can be excluded. In this case as well, the code word in Table 2 is 132, the code word in Table 3 is 520, and 7/8 conversion is performed.

Both 9/1o conversion is possible.

When excluding codewords with F = “1”’ and DP=O,
The output of the ROM 104 is 11 bits, and the output of the ROM 106 is 13 bits, making the D flip-flop 111 unnecessary. Also, the formula (1) giving the select code is the formula (
2) Live a long life.

5C=P1　Dv■P2　−(2) In this way, the code conversion circuit has a simpler configuration.

The memory capacity required (code word only) for the code conversion circuit of the present invention is i278+2910=6 bits, and 16/1
When realizing 8 conversions with one DC free code, the memory capacity required is 216・1B> -i7 compared to 1M bit
Can be done.

Next, FIG. 2 shows an example of the code inversion circuit of the present invention.

The code word sent from the communication path is sent to a serial-to-parallel converter (S/P) 201 and a D flip-flop 202.
The 8-bit signals are combined into an 18-bit (2 words = 8 bits/word + 10 bits/word) parallel signal, and the 8-bit signals are applied to the input terminals of the ROM 203 and the 1O pin/iJROM 204, respectively. Then, a 1o/9 conversion is performed, and each data word corresponding to the input code is decoded.

After this, the 7 bits of ROM 203 and the upper 1 bit of ROM 204 are transferred to the D flip-flop 205.
The remaining 8 bits are taken into D flip-flop 206. The D flip-flop 205 receives the first word during code conversion, and the D flip-flop 206 receives the second word.

The output switching circuit 2 controls the data words decoded in this way to be sequentially sent to the external circuit.
07, and its output [D is connected directly to the output control terminal of the flip-flop 205, while the inverter 2
08', f: Connected to the output control terminal of the D flip-flop 206 through.

As shown above, the code inversion circuit of the present invention can be realized with an extremely simple circuit configuration.

Furthermore, the memory capacity of the ROM required for the code inversion circuit of the present invention is 2.9+27+10.8 bits, which is 16 bits.
/18 conversion DC free one code in one code,
Memory capacity required for ROM of sign inversion circuit: 2181
It can be reduced to about 1/400 compared to 6-4 Mbits.

Furthermore, the present invention divides two data words into the upper 7 bits of the first word, the least significant bit of the first word, and the entire 9 bits of the second word, and converts the codes into each. Since the bit error spreads to other codewords only in the least significant bit of the first word,
The effect of error propagation on the quality of both images is negligible.

Effects of the Invention As shown above, the code conversion method of the present invention has the following effects:
1, has the properties of y and DC free (IDPI i4). A code suitable for high-density recording such as DVTH can be realized with an extremely simple circuit configuration, the capacity of the ROM used can be significantly reduced, and the influence of error propagation can be ignored.

The code conversion method of the present invention having such properties has great practical utility.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a code conversion circuit for implementing the method of the present invention, and FIG. 2 is a block diagram of an inverse code conversion circuit.

Claims (1)

[Claims] (1) For a positive integer i, a data word of Mi bits is defined as M
Convert to a code word of N1 bits which is more dog than i, and get the binary value ゛1
In the Mi7Ni conversion code in which the number of consecutive bits of `` and the number of consecutive bits of the binary value ``OI+ are both greater than or equal to d,
A code conversion method characterized in that a positive integer code of 2 or more and a code of 1 or more are constructed. (2) The code conversion method according to claim 1, wherein the code word length Ni is an even number with respect to i and j. (3) For i and j, all 0 Mi/Ni conversion codes are DC free codes, and the M/N conversion codes are also DC free codes. code conversion method. (4) The code according to claim 3, wherein the control for converting the M/N conversion code into a DC free code is performed in units of Mi/Ni conversion codes for 1 and 3. Conversion method. (5) Ko = 2, d: 1, M, , = 7, Nl:
8, M2=9 and N2-10, the code conversion method according to claim 4. (6) Of the 1e bits of two 8-bit data words, the upper 7 bits of the first data word are converted to 7/8, and the least significant bit of the first data word and the 8 bits of the second data word are converted to 7/8. 6. The code conversion method according to claim 5, wherein 9 bits are converted to 9/10 according to the method. (7) The code conversion method according to claim 5 or 6, characterized in that d=1 and -y. (a) M,/N,=7/8 conversion code is d=1. ni = 6
8. The code conversion method according to claim 7, wherein the code conversion method is a DC free code. (9) The code according to claim 7 or 8, wherein the disparity DP defined by the difference between the number of 1° and “○” in the code word is in the range of IDP1z4. Conversion method. (1o) Claim 7, characterized in that the maximum number of consecutive bits of the same binary value at the beginning of a code word is 3.
9. Code conversion method according to item 8 or 9.