JPS60244872A - Display device for frequency analyzing device - Google Patents

Abstract

PURPOSE:To easily grasp the variation of the peak value in each frequency band by providing a means which displays the peak value of every frequency band and a means which decreases a peak value display successively when the peak value decreases. CONSTITUTION:An acoustic signal amplified by an amplifier 3 is classified by frequency bands through band-pass filters BFP1-BFP7. The classified signals of the respective bands have their levels discriminated through a data selecting circuit 4, comparing circuit 7, etc., and are sent to a control part 5. The control part 5 controls the flashing of a diode matrix 11 according to the signal levels of the respective bands to display the instantaneous levels of the respective frequency bands. The control circuit 5 has a function which detects and displayed variation in the peak value of each frequency band component in every specific time on the matrix part 11 in addition to said function. Consequently, the variation in peak value is grasped easily and sensually.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display device for a frequency analyzer, such as a spectrum analyzer, that displays the level of each frequency band of an acoustic signal.

2. Description of the Related Art Conventional Structures and Problems There have been conventionally known display devices that divide an acoustic signal or the like into frequency band components and display the level of each frequency band component.

However, these conventional display devices only display the instantaneous level of each frequency band component in the form of a bar graph.
There was a drawback that it was not possible to display how the peak value changes for each frequency band.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned conventional drawbacks, and provides a frequency analyzer for use in a frequency analyzer that can display instantaneous level changes of each frequency band component and changes in peak value of each frequency band component at predetermined time intervals. The present invention provides a display device.

Structure of the Invention In order to achieve the above object, the present invention includes means for displaying the peak value for each frequency band, and means for sequentially lowering the peak value display when the peak value decreases. According to the present invention, the state of change in the peak value of each frequency band and the degree of decrease in the peak value can be grasped at a glance.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows a display section of a display device in an embodiment of the present invention. In this example, the acoustic signal is divided into seven frequency bands (
Center frequency 65Hz, 25 Qllz, '500Hz
, IKHz, '1.8KJIz, 4K11z,
i 0KI(z) Divide into K and set the level of each frequency band to 1
Three display elements (such as light emitting diodes) 1 are used to display a bar graph. This embodiment displays the instantaneous level of each frequency band component in the form of a bar graph (blacked out areas in Fig. 1 indicate display elements that emit light), and also displays the instantaneous level of each frequency band component at predetermined time intervals. The peak value at is displayed by light emission (the shaded area in FIG. 1 indicates the light emission of the display element indicating the peak value).

FIG. 2 shows the circuit configuration of this embodiment. In Figure 2, 2 is an adder that adds the right channel signal R and the left channel signal R, 3 is an amplifier that amplifies the added signal, and BPFI to BPF'7 each have a center frequency of 651.
'lz, 25 QHz, 50011z, 1z,
18 times z, 4 times z, 10 times 2 frequency band filter (
band pass filters), 4 are controlled by control signals from the control unit 5, and band pass filters BPFI to BPF
This is a data selection circuit that sequentially selects the output signals of 7 and supplies them to the A/D converter 6. The bandpass filter output selected by the data selection circuit 4 is converted into a digital value by the A/D converter 6. , are input to the comparison circuit 7. In this comparison circuit 7, the output of the A/D converter 6 is compared with 13 different fixed levels, and the comparison results are output. That is, in the comparator circuit 7, the A/D conversion value and 13 fixed levels are compared, and if the A/D conversion value is lower than the fixed level, °H'' is output to the corresponding output terminal. If the A7D conversion value is higher than the fixed level, 'L' is output to the corresponding output terminal. A plurality of outputs (13a) of the comparison circuits 7 are inputted to the control unit 5 via the multiplexer 8. The control unit 5 includes a central processing unit (CPU) and a read-only memory (ROM).

It consists of random access memory (RAM) and the like.

Reference numerals 9 and 10 are driver circuits that supply current to the light emitting diodes constituting the diode matrix circuit 11 to turn on or off the light emitting diodes. The driver circuit 10 sequentially outputs +1H to a plurality of (7) output terminals in a predetermined order according to a control signal output from the control unit 5.
” is output. The diode matrix 11 connected to the intersection of the output terminal of the driver circuit 9 where °'L" is output and the output terminal of the driver circuit 10 where °H" is output intersects. The light emitting diode lights up,
The instantaneous level of each frequency band shown in FIG. 1 is displayed (blacked out areas in FIG. 1). 12 is a demultiplexer, a hold signal output from the control unit 5 is applied to the demultiplexer 12, and a predetermined output terminal of the demultiplexer 12 is output for a predetermined period of time (approximately 2 seconds).
L" is output, the light emitting diode corresponding to the peak value of the diode matrix 11 lights up, and the peak value level is displayed (shaded area in FIG. 1). Furthermore, when the peak value level decreases, the control unit 5 Demultiplexer 12
, a decreasing switching signal is outputted sequentially, and the peak value display is sequentially switched (approximately every 0.1 seconds) in a "raindrop" style. That is,
When the sequential decrease switching signal is applied to the demultiplexer 12, II L II is sequentially applied to the output terminal corresponding to the low level from the output terminal corresponding to the peak value being output.
L'' is output, and the peak value display shown in FIG. 1 is sequentially shifted downward.

FIG. 3 shows functional blocks of the control section 5. As shown in FIG. Third
In the figure, 13 is a previous peak value register in which the previous peak value B is stored, and 14 is a peak value detection means for detecting the peak value of the current level output from the multiplexer 8. The current peak value A detected in is stored in the current peak value register 15.

16 is a comparison means for comparing the previous peak value B and the current peak value A; 17 is a data rewriting means;
As a result of the comparison in step 6, if the current peak value A is larger than the previous peak value B, the data rewriting means 17
The current peak value A is written in place of the peak value B in the previous peak value register 13. 18 is a timer means, and this timer means 18 is compared by the comparison means 16,
If it is determined that the current peak value A is greater than the previous peak value B, a cent is given. While the timer 18 is set (approximately 2 seconds), the hold signal generation means 19 outputs a hold signal, but after 2 seconds have elapsed since the timer 18 was set, the decrease switching signal generation means 20 sequentially outputs a hold signal. A decrease switching signal is output. Note that FIG. 3 only shows functional blocks for peak value display and raindrop display in one band, and in the above embodiment, functional blocks similar to those shown in FIG. 3 are used for seven bands. It's worth it.

FIG. 4 is a flowchart of the functional blocks shown in FIG. 3. In step a, it is determined whether the current peak value A is larger than the previous peak value B. If it is determined that the peak value data is large, a timer is set in step b, and the peak value data is rewritten in step C. When the processing in step C is completed, or in step a, the current peak value A is
If it is determined that the timer is smaller than the previous peak value B, it is determined in step d whether or not 2 seconds have elapsed in the timer that has been sent.If 2 seconds have not elapsed, the process returns to step a, and in step d If it is determined that seconds have elapsed, a sequential switching operation (raindrop display) is performed in step C, and the process returns to step a.

As described above, according to this embodiment, the instantaneous time of each frequency band,
Since the instantaneous level is displayed and the peak value of each frequency band at a predetermined time is displayed, changes in the peak value can be grasped at a glance.

According to this embodiment, when the peak value decreases after a predetermined period of time, the peak value display decreases like a raindrop, so there is an advantage that the degree of change in the peak value can be visually determined.

Effects of the Invention According to the present invention, there is an advantage that not only instantaneous level changes, but also changes in the peak value of each frequency band and the extent of the change in the peak value can be easily grasped.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a display section of a display device for a frequency analyzer according to an embodiment of the present invention, FIG. 2 is a block diagram of the device, and FIG. 3 is a functional block diagram of a part of the control section of the device. The figure shown in FIG. 4 is a flowchart of the same functional blocks. 1... Display element, 2... Adder, 3... Amplifier, B
PF1 to BPF7... Frequency band filter (band pass filter), 4... Data selection circuit, 5... Control unit, 6... A/D converter, 7... Comparison circuit, 8...
・Multiplexer, 9.10...Driver circuit, 11
...Diode matrix, 12... Demultiplexer, 13... Previous peak value register, 14... Peak value detection means, 15... Current peak value register, 16
... Comparison means, 17 ... Data rewriting means, 18
. . . timer means, 19 . . . hold signal generation means, 20 . . . sequential decrease switching signal generation means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure Ro = Co = = Coro = Co ni = Coro: Coro: Coro = Coro = Co: llC: Coro = Coro = Co = Coro = Coro = Kojin: lC: Ko δ Dako EZZ Koro = Koro 5Hx 26;OH
1! ;DOHz IKlh 1. θKlh #Qh I
(lkHz (frequency) Fig. 3 Fig. 4

Claims (1)

[Claims] means for dividing an input signal into a plurality of frequency band components; a display section having a plurality of display elements arranged vertically and horizontally; means for displaying the level of each frequency band component of the input signal on the display section; A display device for a frequency analyzer, comprising means for sequentially switching the lighting of display elements on a lower level side than a signal indicating element to a lower level side.