JPS60220947A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60220947A
JPS60220947A JP7782784A JP7782784A JPS60220947A JP S60220947 A JPS60220947 A JP S60220947A JP 7782784 A JP7782784 A JP 7782784A JP 7782784 A JP7782784 A JP 7782784A JP S60220947 A JPS60220947 A JP S60220947A
Authority
JP
Japan
Prior art keywords
oxidized
region
substrate
oxidation
bird
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7782784A
Other languages
Japanese (ja)
Inventor
Kazuya Kubo
久保 加寿也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7782784A priority Critical patent/JPS60220947A/en
Publication of JPS60220947A publication Critical patent/JPS60220947A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Abstract

PURPOSE:To reduce the length of a bird's beak by a method wherein impurity is introduced only into regions to be selectively oxidized on an Si substrate and the impurity concentration in the Si substrate is allowed to remain unaffected in regions for element formation. CONSTITUTION:An SiO2 film 11 is formed to coat a p type Si substrate 10 equipped with an impurity concentration of 10<15>/cm<2>. B ions are driven into a region 12 to be oxidized for the attainment of a 10<11>/cm<2> concentration for improved conductivity. P ions equal in quantity to the B ions are injected into the edge 13', near the oxidized region 12, of a region 13 not to be oxidized, for neutralization aiming at much lower conductivity. A coating of Si3N4 14 is formed on the regions 13, 13' to be free of oxidation. The entirety is exposed to O2 at high temperatures, when the p<+> layer 12 is oxidized in a short period of time while the neutralized region 13' is very sow in reacting with O2. The result is very short bird's beak fomed of the selectively oxidized region 15, which is useful in the manufacture of highly integrated semiconductor devices.

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は、半導体装置の製造方法に係り、特にシリコン
窒化膜を用いた選択酸化法にお番ノるバーズビーク層の
形状に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to the shape of a bird's beak layer suitable for selective oxidation using a silicon nitride film.

(bl 技術の背景 近年、半導体装置、半導体集積回路装置の集積度は益々
向上し、高集積化されたLSI、VLSIが出現してい
る。
Background of the Technology In recent years, the degree of integration of semiconductor devices and semiconductor integrated circuit devices has been increasingly improved, and highly integrated LSIs and VLSIs have appeared.

このように、高集積化する際の問題点として、半導体ウ
ェハー上に、選択酸化をする際に、必ず生成されるバー
ズビークを如何に小にするかが高築積の大きな課題とな
っており、バーズビークを小にする製造方法が要望され
ている fc] 従来技術と問題点 以下第1図によって、従来の製造方法の概要を説明する
As described above, a major issue in achieving high integration is how to minimize the bird's beaks that are inevitably generated when performing selective oxidation on semiconductor wafers. A manufacturing method that reduces the bird's beak is desired fc] Prior art and problems An outline of the conventional manufacturing method will be explained below with reference to FIG.

図において、1は選択酸化がなされるシリコン基板であ
り、2は酸化シリコン(5i02 )で通常100人程
度の厚みに生成される。
In the figure, 1 is a silicon substrate on which selective oxidation is performed, and 2 is silicon oxide (5i02), which is usually produced to a thickness of about 100 mm.

その上にパターニングで形成され、選択酸化の場合にマ
スクとして使用される窒化シリコン3が形成される。
Silicon nitride 3 is formed thereon by patterning and used as a mask in selective oxidation.

このような構成において、シリコン基板上で酸化膜を生
成する場合には、これを酸化炉内に挿入し、約1気圧の
湿性の酸素気流の雰囲気中におき、酸化温度を1100
℃程度に保持して、数時間の酸化を行なう。
In such a configuration, when forming an oxide film on a silicon substrate, the silicon substrate is inserted into an oxidation furnace, placed in an atmosphere of a humid oxygen stream of approximately 1 atm, and the oxidation temperature is increased to 1100 mA.
Oxidation is carried out for several hours while maintaining the temperature at about ℃.

このようにして生成された酸化シリコン4は、深さが約
4ミクロン程度に形成されることが普通である。
The silicon oxide 4 thus produced is usually formed to a depth of about 4 microns.

このシリコン基板の酸化炉における酸化工程では、シリ
コンと酸素が化学反応によって生成されるため、酸化に
伴って生成される酸化シリコンの体積が膨張して、最初
のシリコン基板の体積に対して酸化シリコンの体積は、
約2倍の体積に膨張する。
In this oxidation process of silicon substrates in an oxidation furnace, silicon and oxygen are produced through a chemical reaction, so the volume of silicon oxide produced during oxidation expands, and the silicon oxide becomes larger than the original silicon substrate volume. The volume of
Expands to about twice its volume.

従って選択酸化部分が酸化膨張すると共に、その生成さ
れた酸化シリコン部の両端においても、順次酸化の影響
を受けるために、この部分でも酸化シリコンが形成され
、所謂バーズビークができる。
Therefore, as the selectively oxidized portion expands due to oxidation, both ends of the silicon oxide portion thus formed are also affected by the oxidation, so that silicon oxide is also formed in these portions, resulting in a so-called bird's beak.

この様にして生成されるバーズビークの形状は、酸化シ
リコンの長さが5μm程度であると、バーズビークの長
さは2乃至3μm程度になるため、このバーズビークの
長さが、最終的に選択酸化する際の限界を決めることに
なる。
The shape of the bird's beak generated in this way is such that if the length of the silicon oxide is about 5 μm, the length of the bird's beak will be about 2 to 3 μm. This will determine the limits.

このような理由から、特に高簗積化が必要な酸化シリコ
ンを選択酸化をする場合には、可能な限すバーズビーク
の形状の小なる酸化法が要望されている。
For these reasons, especially when selectively oxidizing silicon oxide that requires a high slag thickness, there is a demand for an oxidation method that minimizes the bird's beak shape as much as possible.

fd) 発明の目的 本発明は上記従来の欠点に鑑み、シリコンの半導体ウェ
ハー上に選択酸化をする場合に、バーズビークの小なる
形状でシリコン酸化層を形成する方法を提供することを
目的とする (a) 発明の構成 この目的は、本発明によれば、半導体シリコン基板表面
で、酸化領域に基板と同一の導電形の不純物を注入して
導電性を高くし、酸化されない領域であって該酸化領域
周辺に、基板と反対導電形の不純物を注入して導電性を
低くし、該基板上に耐酸化膜を形成して前記酸化領域を
露出し、該酸化領域を酸化することを特徴とする半導体
装置の製造方法を提供することによって達成できる。
fd) Purpose of the Invention In view of the above-mentioned conventional drawbacks, an object of the present invention is to provide a method for forming a silicon oxide layer in a small bird's beak shape when performing selective oxidation on a silicon semiconductor wafer. a) Structure of the Invention According to the present invention, an impurity having the same conductivity type as that of the substrate is implanted into an oxidized region on the surface of a semiconductor silicon substrate to increase the conductivity, and the oxidized region is not oxidized. The method is characterized by implanting impurities of a conductivity type opposite to that of the substrate around the region to lower the conductivity, forming an oxidation-resistant film on the substrate to expose the oxidized region, and oxidizing the oxidized region. This can be achieved by providing a method for manufacturing a semiconductor device.

(fl 発明の実施例 一般に、シリコン基板を酸化させる場合には、そのシリ
コン基板の酸化の時間的進行度合は、その半導体に含ま
れる不純物の多少や、性質には関係がなく、寧ろそのシ
リコン基板の電導性が大きい程、シリコン基板の酸化の
進行の度合が増大する。
(fl Embodiments of the Invention Generally, when a silicon substrate is oxidized, the degree of progress of oxidation of the silicon substrate over time has nothing to do with the amount or nature of impurities contained in the semiconductor, but rather The greater the electrical conductivity of the silicon substrate, the greater the degree of progress of oxidation of the silicon substrate.

本発明は、このシリコン基板の酸化の性質を応用したも
のであり、以下、本発明の実施例を第2図によって詳述
する。
The present invention applies this oxidation property of a silicon substrate, and examples of the present invention will be described in detail below with reference to FIG.

第2図(])はシリコン基板10の上に、通常の酸化法
によって、酸化シリコン膜11を約100人の厚みで形
成する。
In FIG. 2( ), a silicon oxide film 11 is formed to a thickness of about 100 nm on a silicon substrate 10 by a normal oxidation method.

この場合のシリコン基板は、N型でもP型でもいずれの
伝導性シリコン基板にも適用できるが、実施例としてP
型シリコン基板の場合について説明する。
The silicon substrate in this case can be applied to either N-type or P-type conductive silicon substrate, but as an example, P
The case of a type silicon substrate will be explained.

第2図(2)は、不純物濃度が1015cm−3のP型
シリコン基板の表面に、酸化する部分12と酸化しない
部分13とがあるとする。
In FIG. 2(2), it is assumed that there are an oxidized portion 12 and an unoxidized portion 13 on the surface of a P-type silicon substrate with an impurity concentration of 1015 cm-3.

このような場合には、P型シリコン基板の酸化をさせた
い部分に、P型シリコン基板に含まれる不純物(例えば
ボロン)を10” cm−3倍程度のボロン(B)を注
入する。
In such a case, approximately 10" cm -3 times as much boron (B) as the impurity (for example, boron) contained in the P-type silicon substrate is implanted into the portion of the P-type silicon substrate where it is desired to be oxidized.

注入方法は、イオン注入法によって、酸化シリコン11
の表面から、数千人の深さに注入することにより、この
部分は更に伝導性の良いP型シリコンとなる。
The implantation method is silicon oxide 11 by ion implantation.
By implanting the silicon to a depth of several thousand nanometers from the surface, this region becomes more conductive P-type silicon.

一方酸化をさせない部分13のうち酸化部分12に近い
端部13’にのみ、P型シリコン基板に含まれる不純物
(例えばボロン)と反対導電性半導体になるような不純
物(例えば燐)をP型シリコン基板に含まれる不純物の
量と同量だけイオン注入法により添加して、この端部1
3′にはシリコン基板のP型が添加物によって、P型シ
リコンが電気的に中性化された部分を生成させることに
よって、この部分の伝導性は著しく低下する。
On the other hand, an impurity (e.g., phosphorus) that becomes a conductive semiconductor opposite to the impurity (e.g., boron) contained in the P-type silicon substrate is added to the P-type silicon only at the end portion 13' near the oxidized portion 12 of the portion 13 that is not oxidized. The same amount of impurities as that contained in the substrate is added by ion implantation to form this edge 1.
At 3', the P-type silicon of the silicon substrate generates an electrically neutralized portion due to the additive, so that the conductivity of this portion is significantly reduced.

次ぎに第2図(3)のように、酸化シリコンの上の酸化
させない部分13.13′上に、通常の方法によって、
窒化シリコン(Si3 N 4 )膜14を2000人
の厚みで形成する。
Next, as shown in FIG. 2(3), on the unoxidized portions 13 and 13' of the silicon oxide, by the usual method,
A silicon nitride (Si3N4) film 14 is formed to a thickness of 2000 nm.

このように伝導性が増加するような不純物がドープされ
たシリコン基板上に、窒化シリコン膜でマスクされたシ
リコン基板を、酸化炉に入れ、湿性の酸素雰囲気中で、
1100°Cの温度で数時間加熱することにより、伝導
性の高いP型になった部分の酸化が加速されて短時間に
酸化が行われ、反対に不純物がトープされて、電気的に
伝導性が補償されて伝導性が低下した部分は、酸化が著
しく遅くなってしまうため、酸化される部分の形状は、
第2図(4)の如(生成される酸化シリコンのバーズビ
ーク15は、生成された酸化シリコンの厚みに比較して
、バーズビークの長さが非常に小に形成される。
A silicon substrate doped with an impurity that increases conductivity is masked with a silicon nitride film, and then placed in an oxidation furnace in a humid oxygen atmosphere.
By heating at a temperature of 1100°C for several hours, the oxidation of the highly conductive P-type portion is accelerated and oxidized in a short period of time, while impurities are toped and become electrically conductive. The shape of the oxidized part is
As shown in FIG. 2 (4), the bird's beak 15 of silicon oxide that is generated has a very small length compared to the thickness of the silicon oxide that is generated.

以上の例におけるシリコン基板上の選択酸化のバーズビ
ークの寸法は、従来の方法に比較すると、同様の厚みの
酸化シリコンの生成した場合に比較して、約2/3の長
さのバーズビークの長さになる。
In the above example, the length of the bird's beak of selective oxidation on the silicon substrate is about 2/3 of the length of the bird's beak when silicon oxide of a similar thickness is produced when compared with the conventional method. become.

このことは、予めバターニングする場合のマスクに対し
てバーズビークの長さが小になるだけ、シリコン基板上
での素子の集積度を向上させることができる。
This makes it possible to improve the degree of integration of elements on the silicon substrate by reducing the length of the bird's beak with respect to a mask that is patterned in advance.

fgl 発明の効果 以上詳細に説明したように、本発明のバーズビークの寸
法を小にする製造方法を採用することにより、高集積度
の半導体装置の製作に供し得ることができ効果大なるも
のがあり、特に本発明ではバーズビークの問題となる部
分にのみ不純物を導入し、後に素子が形成される部分は
基板の不純物濃度を維持させることができる。
fgl Effects of the Invention As explained in detail above, by adopting the manufacturing method of the present invention for reducing the size of the bird's beak, it is possible to manufacture highly integrated semiconductor devices, and there are great effects. In particular, in the present invention, impurities are introduced only into the areas where the bird's beak is a problem, and the impurity concentration of the substrate can be maintained in areas where elements will be formed later.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の選択酸化の説明図、第2図は本発明の選
択酸化の説明図である。 図において、1.10は選択酸化をするシリコン基板、
2.11は酸化シリコン、3.14は窒化シリコン、4
.15は選択酸化物の形成部分、12は酸化をさせる部
分、13は酸化をさせない部分、13′は周辺部である
。 第1 第2
FIG. 1 is an explanatory diagram of conventional selective oxidation, and FIG. 2 is an explanatory diagram of selective oxidation according to the present invention. In the figure, 1.10 is a silicon substrate subjected to selective oxidation;
2.11 is silicon oxide, 3.14 is silicon nitride, 4
.. Reference numeral 15 designates a portion where a selective oxide is formed, 12 a portion to be oxidized, 13 a portion not to be oxidized, and 13' a peripheral portion. 1st 2nd

Claims (1)

【特許請求の範囲】[Claims] 半導体シリコン基板表面で、酸化領域に基板と同一の導
電形の不純物を注入して導電性を高くし、酸化されない
領域であって該酸化領域周辺に、基板と反対導電形の不
純物を注入して導電性を低くし、該基板上に耐酸化膜を
形成して前記酸化領域を露出し、該酸化領域を酸化する
ことを特徴とする半導体装置の製造方法。
On the surface of a semiconductor silicon substrate, an impurity of the same conductivity type as that of the substrate is implanted into an oxidized region to increase the conductivity, and an impurity of the opposite conductivity type to that of the substrate is implanted into a region that will not be oxidized and around the oxidized region. 1. A method of manufacturing a semiconductor device, comprising lowering the conductivity, forming an oxidation-resistant film on the substrate to expose the oxidized region, and oxidizing the oxidized region.
JP7782784A 1984-04-17 1984-04-17 Manufacture of semiconductor device Pending JPS60220947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7782784A JPS60220947A (en) 1984-04-17 1984-04-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7782784A JPS60220947A (en) 1984-04-17 1984-04-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60220947A true JPS60220947A (en) 1985-11-05

Family

ID=13644869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7782784A Pending JPS60220947A (en) 1984-04-17 1984-04-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60220947A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091331A (en) * 1990-04-16 1992-02-25 Harris Corporation Ultra-thin circuit fabrication by controlled wafer debonding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091331A (en) * 1990-04-16 1992-02-25 Harris Corporation Ultra-thin circuit fabrication by controlled wafer debonding

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