JPS60207350A - Adjusting method of wafer dicing line angle - Google Patents

Adjusting method of wafer dicing line angle

Info

Publication number
JPS60207350A
JPS60207350A JP6220884A JP6220884A JPS60207350A JP S60207350 A JPS60207350 A JP S60207350A JP 6220884 A JP6220884 A JP 6220884A JP 6220884 A JP6220884 A JP 6220884A JP S60207350 A JPS60207350 A JP S60207350A
Authority
JP
Japan
Prior art keywords
angle
dicing line
adjusting
compensation value
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6220884A
Other languages
Japanese (ja)
Other versions
JPH0680727B2 (en
Inventor
Hisaya Suzuki
Makoto Arie
Original Assignee
Toshiba Seiki Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Seiki Kk filed Critical Toshiba Seiki Kk
Priority to JP6220884A priority Critical patent/JPH0680727B2/en
Publication of JPS60207350A publication Critical patent/JPS60207350A/en
Publication of JPH0680727B2 publication Critical patent/JPH0680727B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

PURPOSE:To enable adjusting of angle perfectly and precisely by automatically adjusting the dicing line angle of a wafer based on the detection results of a camera using each compensation value. CONSTITUTION:In the case of recognizing the position of coordinates of each pellet 22 on an X-Y table 21, a camera 77 detects the dicing line 39 of a wafer 35, the angle of the dicing line 39 against X-Y directions is compared with a reference alignment angle and the water 35 is aligned with the reference alignment angle calculating the compensation value (thetaK1) of the angle. The adjustment with the reference alignment angle is confirmed after the angle is compensated with the compensation value (thetaK1). Consequently, compensation of angle is carried out based on a compensation value (thetaK2) of angle calculated, if necessary. This enables the wafer 35 aligned on the X-Y table 21 perfectly and precisely.
JP6220884A 1984-03-31 1984-03-31 Pellet bonding machine Expired - Fee Related JPH0680727B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6220884A JPH0680727B2 (en) 1984-03-31 1984-03-31 Pellet bonding machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6220884A JPH0680727B2 (en) 1984-03-31 1984-03-31 Pellet bonding machine

Publications (2)

Publication Number Publication Date
JPS60207350A true JPS60207350A (en) 1985-10-18
JPH0680727B2 JPH0680727B2 (en) 1994-10-12

Family

ID=13193490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6220884A Expired - Fee Related JPH0680727B2 (en) 1984-03-31 1984-03-31 Pellet bonding machine

Country Status (1)

Country Link
JP (1) JPH0680727B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017011121A (en) * 2015-06-23 2017-01-12 三星ダイヤモンド工業株式会社 Scribe device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771146A (en) * 1980-10-21 1982-05-01 Toshiba Corp Dicing apparatus for semiconductor wafer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771146A (en) * 1980-10-21 1982-05-01 Toshiba Corp Dicing apparatus for semiconductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017011121A (en) * 2015-06-23 2017-01-12 三星ダイヤモンド工業株式会社 Scribe device

Also Published As

Publication number Publication date
JPH0680727B2 (en) 1994-10-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees