JPS60200227A - Thin-film nonlinear resistance element for display device - Google Patents

Thin-film nonlinear resistance element for display device

Info

Publication number
JPS60200227A
JPS60200227A JP59055359A JP5535984A JPS60200227A JP S60200227 A JPS60200227 A JP S60200227A JP 59055359 A JP59055359 A JP 59055359A JP 5535984 A JP5535984 A JP 5535984A JP S60200227 A JPS60200227 A JP S60200227A
Authority
JP
Japan
Prior art keywords
layer
nonlinear resistance
thin film
resistance element
film nonlinear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59055359A
Other languages
Japanese (ja)
Inventor
Kanetaka Sekiguchi
金孝 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Original Assignee
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to JP59055359A priority Critical patent/JPS60200227A/en
Publication of JPS60200227A publication Critical patent/JPS60200227A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1365Active matrix addressed cells in which the switching element is a two-electrode device

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To increase the threshold voltage of a nonlinear resistance element and to improve display quality, and to stabilize characteristics and to prevent the deterioration by forming >=2 kinds of metallic layer between stacked thin-film nonlinear resistance elements. CONSTITUTION:A display electrode layer 23 and a light shield layer 33 are provided on a substrate 31, and then a lower rectifying connection part 34 is provided. A lower metallic short-circuit layer 35 and an upper metallic short-circuit layer 35 are provided on the connection part 34, and an upper rectifying connection part 37 is provided on the short-circuit layer 36. Further, a deterioration prevention layer 38 for the rectifying connection parts, an interlayer insulation layer 39, and a mutual wiring layer 40 are provided on the connection part 37. Thus, the threshold voltage of the rectifying connection parts is increased to improve the display quality, and the adhesive strength between the rectifying connection parts and metallic layers is improved to stabilize the characteristics and prevent the deterioration.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、閾値電圧の大きい表示用非線形抵抗素子を効
率よく形成するためのものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is for efficiently forming a display nonlinear resistance element with a large threshold voltage.

〔発明の背景〕[Background of the invention]

液晶、EL、EC,FDP、螢光表示等の各i 。 Liquid crystal, EL, EC, FDP, fluorescent display, etc.

表示装置はいずれも実用化段階忙達し、現在の目標は高
密度なマトリクス型表示にあるといえる。
All display devices have reached the stage of practical use, and the current goal is to create a high-density matrix type display.

マトリクス駆動に問題のある表示においては、能動付加
素子を用いた所謂「アクティブ・マトリクス」法が有効
である。
For displays where matrix driving is problematic, a so-called "active matrix" method using active additive elements is effective.

表示装置に薄膜非線形抵抗素子を用いる事により、高密
度、高画質の表示が可能であり、薄膜非線形抵抗素子(
薄膜整流素子)が表示装置用能動付加素子として勝れて
いる事は前出願(特願昭57−167945号)に記載
ずみである。さらに、薄膜非線形抵抗素子の駆動能力を
増すためには、薄膜非線形抵抗素子の閾値電圧(vth
)を大きくする必要がある。この点についても前出願(
特願昭57−16794号)に記載ずみである。
By using thin-film nonlinear resistance elements in display devices, high-density, high-quality displays are possible.
The superiority of the thin film rectifying element as an active addition element for display devices has been described in a previous application (Japanese Patent Application No. 167945/1983). Furthermore, in order to increase the driving ability of the thin film nonlinear resistance element, the threshold voltage (vth
) needs to be increased. Regarding this point, the previous application (
It is described in Japanese Patent Application No. 57-16794).

本発明は、薄膜非線形抵抗素子を縦接続(重ね合わせる
)する際に生ずる逆整流接合部を短絡するために、逆整
流性接続部に金属層を導入するものであり、かつ、その
金属層が少なくても2種類以上の金属層を有するもので
ある。金属層を複数層にする事により、薄膜非線形抵抗
素子との密着の改善ができ、エツチング等による金属層
と薄膜非線形抵抗素子間のサイドエツチング量も減少で
き、金属層と薄膜非線形抵抗素子間との拡散等がコント
ロール可能になり、薄膜非線形抵抗素子の劣化防止及び
耐熱性の向上ができる。
The present invention introduces a metal layer into the reverse rectifying connection part in order to short-circuit the reverse rectifying joint part that occurs when thin film nonlinear resistance elements are vertically connected (superimposed), and the metal layer is It has at least two or more types of metal layers. By having multiple metal layers, it is possible to improve the adhesion with the thin film nonlinear resistance element, reduce the amount of side etching between the metal layer and the thin film nonlinear resistance element due to etching, etc., and reduce the amount of side etching between the metal layer and the thin film nonlinear resistance element. This makes it possible to control the diffusion, etc. of the thin film nonlinear resistance element, thereby preventing deterioration and improving heat resistance of the thin film nonlinear resistance element.

〔従来技術と問題点〕[Conventional technology and problems]

第1図は、薄膜非線形抵抗素子の整流接続部を2段に重
ね、かつ、重ねた間に金属層を形成した例である。第1
図において、1は基板、2は表示電極、6は光シールド
層、4は薄膜非線形抵抗素子の下側の整流接続部、5は
、上下整流接続部を短絡する金属層、6は、上側の整流
接続部、8は整流接続部の劣化防止層及びエツチングの
際のマスキングを兼ねた膜であり、8は層間絶縁膜、9
は、相互配線層である。
FIG. 1 shows an example in which rectifying connection portions of thin film nonlinear resistance elements are stacked in two stages, and a metal layer is formed between the stacks. 1st
In the figure, 1 is a substrate, 2 is a display electrode, 6 is a light shield layer, 4 is a lower rectifier connection of a thin film nonlinear resistance element, 5 is a metal layer that short-circuits the upper and lower rectifier connections, and 6 is an upper rectifier connection. A rectifier connection portion, 8 is a film that serves as a deterioration prevention layer for the rectification connection portion and a masking during etching, 8 is an interlayer insulating film, 9
is an interconnection layer.

第1図は、理想的な構造を示す図であるが、実際の場合
、いくつかの問題がある。その例を第2図及び第3図に
示した。第2図は、上、下の整流接続部と短絡層との密
着が悪く、サイドエツチングが進行した図である。この
サイドエツチングにより、層間絶縁層の耐圧減少、配線
層と素子との短絡、あるいは、配線の断線が生じ、素子
ノ(ラツキ及び表示欠陥が起こり、表示品質の低下につ
ながる。
Although FIG. 1 shows an ideal structure, there are some problems in actual use. Examples are shown in FIGS. 2 and 3. FIG. 2 is a diagram showing poor adhesion between the upper and lower rectifying connection portions and the shorting layer, and side etching has progressed. This side etching causes a reduction in the withstand voltage of the interlayer insulating layer, a short circuit between the wiring layer and the element, or a disconnection of the wiring, which causes element irregularities and display defects, leading to a deterioration in display quality.

第3図は、上整流接続部をエツチングする際に、整流接
続部を構成する層のエツチング速度の)くラツキ、ピン
ホール成るいは、短絡層のピンホールが発生した図であ
り、この結果、表示電極層の劣化、基板の白濁及び、断
差Q)発生等が生じてしまい、表示品質の低下につなが
る。第2図において10は、基板、11は表示電極、1
2は光シールド層、16は下側の整流接続部、14は上
下整流接続部を短絡する金属層、15は上側の整流接続
部、16は整流接続部の劣化防止層、17.18は、サ
イドエツチング部分を表わしている。
Figure 3 is a diagram showing that when etching the upper rectifying connection, variations in the etching speed of the layer constituting the rectifying connection, pinholes, or pinholes in the shorting layer occurred; , deterioration of the display electrode layer, clouding of the substrate, generation of a difference Q), etc. occur, leading to deterioration of display quality. In FIG. 2, 10 is a substrate, 11 is a display electrode, 1
2 is a light shield layer, 16 is a lower rectifier connection, 14 is a metal layer that short-circuits the upper and lower rectifier connections, 15 is an upper rectifier connection, 16 is a deterioration prevention layer for the rectifier connection, 17.18 is, It shows the side etching part.

第3図において、21は基板、22は表示電極、26は
光シールド層、24は下側の整流接続部、25は上下整
流接続部を短絡する金属層、26は上側の整流接続部、
27は整流接続部の劣化防止層、28は、短絡層のダメ
ージを受けた部分である。
In FIG. 3, 21 is a substrate, 22 is a display electrode, 26 is a light shield layer, 24 is a lower rectifier connection, 25 is a metal layer that short-circuits the upper and lower rectifier connections, 26 is an upper rectifier connection,
27 is a deterioration prevention layer of the rectifying connection portion, and 28 is a damaged portion of the short circuit layer.

〔発明の目的〕[Purpose of the invention]

本発明は、第1図、第2図の如き表示品質の低下に寄与
するものを短絡層を多層にする事により除去し、かつ、
各層を薄膜化し、素子の厚さ及びエツチング時間の増加
等もまねく事なく、形成も同−真空内で鐘続形成可能な
ため、工程上の負荷を増す事なく表示品質の向上ができ
る非線形抵抗素子を提供することを目的とする。
The present invention eliminates what contributes to the deterioration of display quality as shown in FIGS. 1 and 2 by using multiple shorting layers, and
Each layer is made thinner, without increasing the element thickness or etching time, and can be formed in succession in a vacuum. Nonlinear resistors improve display quality without increasing process load. The purpose is to provide an element.

〔発明の実施例〕[Embodiments of the invention]

第4図は、本発明を利用した実施例である。短絡層を2
層にする事により上下整流接続部で独立に密着力の向上
ができ、サイドエツチングの減少が可能となり、かつ、
整流接続部の構成する層のエツチングの停止層を形成で
きるため、表示電極層の劣化もなく、理想的な構造の素
子の形成が可能となる。その構成は第4図の如き素子と
なる。
FIG. 4 shows an embodiment using the present invention. 2 short circuit layers
By layering, it is possible to improve the adhesion force independently at the upper and lower rectifying connection parts, and it is possible to reduce side etching.
Since an etching stopper layer can be formed for the layer constituting the rectifying connection portion, an element with an ideal structure can be formed without deterioration of the display electrode layer. Its structure is an element as shown in FIG.

第4図において、61は基板、62は表示電極層、66
は光シールド層、64は下側の整流接続部、65は下層
短絡層、66は上層短絡層、67は上側の整流接続部、
68は整流接続部の劣化防止層、69は層間絶縁層、4
0は相互配線層である。
In FIG. 4, 61 is a substrate, 62 is a display electrode layer, and 66
is a light shield layer, 64 is a lower rectifying connection part, 65 is a lower shorting layer, 66 is an upper shorting layer, 67 is an upper rectifying connection part,
68 is a deterioration prevention layer of the rectifier connection portion, 69 is an interlayer insulating layer, 4
0 is an interconnection layer.

第5図は、本発明を利用し、短絡層を3層にした例であ
る。3層構造にする事により、上下の整流接続部との電
気的接触及び、物理的密着力の改良と、上側の整流接続
部を構成する層のエツチングの停止層を独立に形成でき
、薄膜非線形抵抗素子の特性の安定化及び、劣化の防止
、バラツキの減少が可能となり、表示装置の見映えの向
」二になる第5図は短絡層を三層にした場合の実施例で
ある。
FIG. 5 shows an example in which the present invention is utilized and the number of shorting layers is three. The three-layer structure improves electrical contact and physical adhesion with the upper and lower rectifier connections, and allows the formation of an independent etching stopper layer for the upper rectifier connection, reducing thin film nonlinearity. It is possible to stabilize the characteristics of the resistive element, prevent deterioration, and reduce variations, thereby improving the appearance of the display device. FIG. 5 shows an example in which the shorting layer is made of three layers.

第5図において、51は基板、52は表示電極、53は
光シールド層、54は下側の整流接続部、55は下層の
短絡層、56は中間の短絡層、57は上層の短絡層、5
8は上側の整流接続部、59は整流接続部の劣化防止層
、60は層間絶縁層、61は相互配線層である。
In FIG. 5, 51 is a substrate, 52 is a display electrode, 53 is a light shield layer, 54 is a lower rectifying connection part, 55 is a lower shorting layer, 56 is an intermediate shorting layer, 57 is an upper shorting layer, 5
Reference numeral 8 designates an upper rectification connection portion, 59 a deterioration prevention layer for the rectification connection portion, 60 an interlayer insulating layer, and 61 an interconnection layer.

以上より明らかな如く、本発明は、複数個重ね合わせに
形成されている多層薄膜非線形抵抗素子において、重ね
合わせた薄膜非線形抵抗素子間(薄膜非線形抵抗素子の
整流接続部間)に2種類以上の金属層を形成する事によ
り、薄膜非線形抵抗素子の閾値電圧を大きくでき1表示
品質の向上ができ、かつ、各金属層と薄膜非線形抵抗素
子との密着力が向上するので、サイドエツチングが減少
し、理想構造に近似な構造が可能となり、かつ、−E層
薄膜非線形抵抗素子構成膚をエツチングする際の下地層
のダメージが防止でき、薄膜非線形抵抗素子の特性の安
定化、劣化の防止、バラツキの減少が可能となり、表示
装置の見映えの向上になる。
As is clear from the above, the present invention provides a multilayer thin film nonlinear resistance element in which a plurality of multilayer thin film nonlinear resistance elements are formed in a stacked manner. By forming a metal layer, the threshold voltage of the thin film nonlinear resistance element can be increased, thereby improving the display quality.In addition, the adhesion between each metal layer and the thin film nonlinear resistance element is improved, so side etching is reduced. , a structure close to the ideal structure is possible, and damage to the underlying layer when etching the E-layer thin film nonlinear resistance element structure can be prevented, and the characteristics of the thin film nonlinear resistance element are stabilized, deterioration is prevented, and variations are prevented. This makes it possible to reduce the amount of noise and improve the appearance of the display device.

以下に実施例を用いて本発明を説明する。The present invention will be explained below using examples.

第6図は、本発明の薄膜非線形抵抗素子の整流接続部が
半導体層のP型半導体層、低不純物濃度の■型半導体層
、N型半導体層から成るPIN接合の2層構造から成り
、PINとPINの間に2層金属層を形成した2層薄膜
非線形抵抗素子の製造工程を表わしている。第6図fA
+は基板上へ透明電極層(表示電極層)及び光シールド
層、下側のPIN型ダイオード層(整流接合部)、下層
及び上層のPIN型ダイオード間に2種類の金属層、及
び上層のPIN型ダイオード層さらに、エツチング成る
いはフォ) IJソ工程による半導体層の劣化を防止す
るための金属層も形成しである。第6図(A)において
71はガラス成るいはセラミック基板、72は表示電極
層でITO成るいは、5n02成るいは薄膜金属膜であ
る。73は光シールド層であり、C「、Ni成るいは、
A7である。74はP型半導体層であり、不純物として
B(ボロン)がドーピングしであるアモーファスシリコ
ンである。75は不純物濃度の低いI型半導体層であり
、65はN型半導体層であり、不純物としてP(リン)
がドーピングしであるアモーファスシリコンである。7
7は下層金属層であり、Ta、Mo、Cr%N i、w
、Al成るいは、Pi等である。78上層金属層であり
、Cr、Ni成るいはA1等である。79はP型半導体
層であり、80はI型半導体層であり、81はN型半導
体層であり、アモーファスシリコンかう成っている。
FIG. 6 shows that the rectifying connection part of the thin film nonlinear resistance element of the present invention has a two-layer structure of a PIN junction consisting of a P-type semiconductor layer, a ■-type semiconductor layer with a low impurity concentration, and an N-type semiconductor layer. This shows the manufacturing process of a two-layer thin film nonlinear resistance element in which two metal layers are formed between PIN and PIN. Figure 6 fA
+ is a transparent electrode layer (display electrode layer) and a light shield layer on the substrate, a lower PIN type diode layer (rectifying junction), two types of metal layers between the lower and upper layer PIN type diodes, and an upper layer PIN. In addition to the diode layer, a metal layer is also formed to prevent deterioration of the semiconductor layer due to etching or IJ process. In FIG. 6(A), 71 is a glass or ceramic substrate, and 72 is a display electrode layer made of ITO, 5N02, or a thin metal film. 73 is a light shield layer made of C'', Ni or
It is A7. 74 is a P-type semiconductor layer, which is amorphous silicon doped with B (boron) as an impurity. 75 is an I-type semiconductor layer with a low impurity concentration, 65 is an N-type semiconductor layer, and P (phosphorus) is added as an impurity.
is amorphous silicon which is not doped. 7
7 is a lower metal layer, consisting of Ta, Mo, Cr%Ni, w
, Al, Pi, etc. 78 is an upper metal layer and is made of Cr, Ni, A1, etc. 79 is a P-type semiconductor layer, 80 is an I-type semiconductor layer, and 81 is an N-type semiconductor layer, which are made of amorphous silicon.

82は、半導体層の安定化及びエツチング、フォトリソ
工程による半導体層の劣イヒな防止するための保護層で
あり、Al成るいはCrである。
A protective layer 82 is made of Al or Cr for stabilizing the semiconductor layer and preventing deterioration of the semiconductor layer due to etching and photolithography processes.

第6図(B)は、第6図(A)までに形成された層を所
定の大きさにパターニングした図である。
FIG. 6(B) is a diagram in which the layers formed up to FIG. 6(A) are patterned to a predetermined size.

第6図(qは、本発明を用いて形成した薄膜非線形抵抗
素子である。第6図(qは、層間絶縁膜として、S i
02.Si、N4、ポリイミード樹脂等を形成した後に
所定の位置にコンタクトホールな形成し、配糊層として
Al成るいは、Cr、NiCr、成るいは多層金属層を
形成後パターニングしたものである。第6図(Qにおい
て、83は層間絶縁膜、84は配線層である。第6図(
qの素子と各表示媒体を組み合わせる事により高密度で
高品質の表示装置の形成ができる。半導体層の形成法は
、プラズマCVD法のみならず、光CVD法、スパッタ
法、蒸着法、イオンブレーティング法が有効である。半
導体の種類は、アモーファス・シリコン、微結晶シリコ
ン、シリコンカーバイド、シリコンゲルマニウム、シリ
コンナイトライドがある。アモ−7アス・シリコンは薄
膜にもかかわらず価電子制御ができるため半導体として
格好の材料である。必要に応じてB、P%H1N、0、
C,Ge。
FIG. 6 (q is a thin film nonlinear resistance element formed using the present invention. FIG. 6 (q is an interlayer insulating film, Si
02. After forming Si, N4, polyimide resin, etc., a contact hole is formed at a predetermined position, and a glue layer of Al, Cr, NiCr, or a multilayer metal layer is formed and then patterned. FIG. 6 (In Q, 83 is an interlayer insulating film, and 84 is a wiring layer.
By combining the q elements and each display medium, a high-density, high-quality display device can be formed. Effective methods for forming the semiconductor layer include not only the plasma CVD method but also the photo CVD method, sputtering method, vapor deposition method, and ion blating method. Types of semiconductors include amorphous silicon, microcrystalline silicon, silicon carbide, silicon germanium, and silicon nitride. Amorphous silicon is a suitable material for semiconductors because it can control valence electrons even though it is a thin film. B, P%H1N, 0, as necessary
C, Ge.

Sn、A7%L1、As等を添加してもよい。Sn, A7%L1, As, etc. may be added.

〔発明の効果〕〔Effect of the invention〕

以上の如く、表示装置用多層薄膜非線形抵抗素子におい
て、重ね合わせた薄膜非線形抵抗素子間[2種以上の金
属層を形成する事により、素子の安定性及び歩留り率が
向上し、表示の均一な表示品質の優れた表示装置の製造
ができる。また金属層は同一真空装置内で形成可能であ
り、製造工程を増す事なく、経済的にも優れている。
As described above, in multilayer thin film nonlinear resistance elements for display devices, by forming two or more metal layers between the superimposed thin film nonlinear resistance elements, the stability and yield rate of the element are improved, and the display is uniform. A display device with excellent display quality can be manufactured. Furthermore, the metal layer can be formed within the same vacuum device, which is advantageous economically without increasing the number of manufacturing steps.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の薄膜非線形抵抗素子の構造を示す部分
断面図である。第2図は、従来の非線形抵抗素子の製造
主りを示し、上、下の薄膜非線形抵抗素子と短絡層との
密着力が悪く、サイドエツチングが進行した部分断面図
である。第3図は、従来の非線形抵抗素子の製造工程に
於ける上側の薄膜非線形抵抗素子をエツチングする際に
短絡層へ与えるダメージを示した部分断面図である。第
4図は、本発明の非線形抵抗素子の構造を示す短絡層を
2層にした部分断面図である。第5図は、。 本発明の非線形抵抗素子の構造を示し短絡層を3層にし
、下層と上層が同一金属で中間層が異種金属である場合
を示した部分断面図である。第6図は、本発明の実施例
で非線形抵抗素子の製造工程を示す部分断面図である。 1.10.21.61.51.71・・・・・・基板、
2.11.22.62.52.72・・・・・・表示電
極、 4.13.24.64.54.6.15.26.67.
58・・・・・・薄膜非線形抵抗素子、7.16.27
.68.59.82・・・・・・劣化防止層、 8.69.60.86・・・・・・層間絶縁膜、9.4
0.61.84・・・・・・相互配線層、5.14.2
5.65.66.55.56.57.77.78・・・
・・・短絡層。 第2図 第3図 第4図 第5図
FIG. 1 is a partial cross-sectional view showing the structure of a conventional thin film nonlinear resistance element. FIG. 2 is a partial sectional view showing the method of manufacturing a conventional nonlinear resistance element, in which the adhesion between the upper and lower thin film nonlinear resistance elements and the shorting layer was poor, and side etching progressed. FIG. 3 is a partial cross-sectional view showing damage caused to the shorting layer when etching the upper thin film nonlinear resistance element in the conventional manufacturing process of the nonlinear resistance element. FIG. 4 is a partial cross-sectional view showing the structure of the nonlinear resistance element of the present invention, in which the shorting layer is made up of two layers. Figure 5 shows. FIG. 2 is a partial cross-sectional view showing the structure of the nonlinear resistance element of the present invention, in which the shorting layer has three layers, the lower layer and the upper layer are of the same metal, and the intermediate layer is of different metals. FIG. 6 is a partial cross-sectional view showing the manufacturing process of a nonlinear resistance element according to an embodiment of the present invention. 1.10.21.61.51.71...Substrate,
2.11.22.62.52.72...Display electrode, 4.13.24.64.54.6.15.26.67.
58... Thin film nonlinear resistance element, 7.16.27
.. 68.59.82...Deterioration prevention layer, 8.69.60.86...Interlayer insulating film, 9.4
0.61.84...Interconnection layer, 5.14.2
5.65.66.55.56.57.77.78...
...Short layer. Figure 2 Figure 3 Figure 4 Figure 5

Claims (3)

【特許請求の範囲】[Claims] (1)表示装置用薄膜非線形素子が、複数個重ね合わせ
に形成されている多層薄膜非線形抵抗素子において、重
ね合わせた薄膜非線形抵抗素子間に少なくても2種類以
上の金属層を有する事を特徴とする表示装置用薄膜非線
形抵抗素子。
(1) A thin film nonlinear element for a display device is a multilayer thin film nonlinear resistance element formed by stacking a plurality of thin film nonlinear resistance elements, and is characterized by having at least two or more types of metal layers between the stacked thin film nonlinear resistance elements. Thin film nonlinear resistance element for display devices.
(2) 重ね合わせた薄膜非線形抵抗素子間の金属層が
、3層構造から成り、下層より、1層目と3層目が同一
金属で、2層目の中間層が異種金属である事を特徴とす
る特許請求の範囲第1項記載の表示装置用薄膜非線形抵
抗素子。
(2) The metal layer between the stacked thin film nonlinear resistance elements has a three-layer structure, and from the bottom, the first and third layers are made of the same metal, and the second intermediate layer is made of a different metal. A thin film nonlinear resistance element for a display device according to claim 1.
(3)薄膜非線形抵抗素子がアモーファスシリコンであ
る事を特徴とする特許請求の範囲第1項記載の表示装置
用薄膜非線形抵抗素子。
(3) The thin film nonlinear resistance element for a display device according to claim 1, wherein the thin film nonlinear resistance element is made of amorphous silicon.
JP59055359A 1984-03-23 1984-03-23 Thin-film nonlinear resistance element for display device Pending JPS60200227A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59055359A JPS60200227A (en) 1984-03-23 1984-03-23 Thin-film nonlinear resistance element for display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59055359A JPS60200227A (en) 1984-03-23 1984-03-23 Thin-film nonlinear resistance element for display device

Publications (1)

Publication Number Publication Date
JPS60200227A true JPS60200227A (en) 1985-10-09

Family

ID=12996293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59055359A Pending JPS60200227A (en) 1984-03-23 1984-03-23 Thin-film nonlinear resistance element for display device

Country Status (1)

Country Link
JP (1) JPS60200227A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738513A (en) * 1985-03-22 1988-04-19 Fuji Electric Co., Ltd. Liquid crystal display including a non-linear resistance element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738513A (en) * 1985-03-22 1988-04-19 Fuji Electric Co., Ltd. Liquid crystal display including a non-linear resistance element

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