JPS6017934A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6017934A JPS6017934A JP58125304A JP12530483A JPS6017934A JP S6017934 A JPS6017934 A JP S6017934A JP 58125304 A JP58125304 A JP 58125304A JP 12530483 A JP12530483 A JP 12530483A JP S6017934 A JPS6017934 A JP S6017934A
- Authority
- JP
- Japan
- Prior art keywords
- carrier
- semiconductor device
- chip
- mother board
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置に係り、特に、パッケージの一種
として広く用いられているチップキャリアと、該チップ
ギヤリアが装着されるマザーボードとの実装体に関する
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices, and more particularly to a package of a chip carrier widely used as a type of package and a motherboard to which the chip gear carrier is mounted.
従来例の構成とその問題点
従来は、第１図に示すように、たとえば、半導体チップ
１をチップキャリア２内に組立てた後、まず、融点温度
が２８０°Ｃ程度の金−錫合金の、２ ′
いわゆる高融点半田３を用いて、金属板キャップ４を封
止し、次に、マザーボード６」二に、融点温度が１８０
℃程度の通常よく用いられる半［ｆｌ、即ち、鉛−錫の
合金半［ｒ−１を用いて、同チップキャリア２を貫通し
て外部に取り出されたリード部に接続電極６を形成して
いた。なお、７はワイヤーを示す。一方、こうｌ−だ半
導体装置がよく用いられている実状に並行して安価な半
導体装置を得るために、また、これらを具現するための
製造工程の簡素化が重重れていた。Conventional Structure and Problems Conventionally, as shown in FIG. 1, for example, after assembling a semiconductor chip 1 into a chip carrier 2, a gold-tin alloy having a melting point temperature of about 280° C. 2' The metal plate cap 4 is sealed using a so-called high melting point solder 3, and then the motherboard 6' is soldered to a solder with a melting point temperature of 180℃.
The connection electrode 6 is formed on the lead part that penetrates the chip carrier 2 and is taken out to the outside using a commonly used half [fl, that is, a lead-tin alloy half [r-1] at a temperature of about °C. Ta. Note that 7 indicates a wire. On the other hand, in parallel with the fact that such large-sized semiconductor devices are often used, it has become important to obtain inexpensive semiconductor devices and to simplify the manufacturing process for realizing these devices.
発明の目的
本発明は、上記の要請に鑑がみてなされたものであって
、マザーボードがチップキャリアの封止蓋の機能をも有
した半導体装置を提供することを目的とする〇
発明の構成
本発明は、チップキャリアをマザーボードに装着する実
装体において、前記マザーボードは、前記チップキャリ
アの支持体および電極を受ける構造体に加えて、前記チ
ップギヤリアの封止蓋の機３１・コ・
能をもった半導体装置であり、これによれば、安価な半
導体装置が（１られるものとなる。Purpose of the Invention The present invention has been made in view of the above requirements, and an object of the present invention is to provide a semiconductor device in which the motherboard also functions as a sealing lid for a chip carrier. The invention provides a mounting body in which a chip carrier is attached to a motherboard, in which the motherboard has a function of a sealing lid for the chip gear rear in addition to a structure for receiving the support and electrodes of the chip carrier. This is a semiconductor device, and according to this, an inexpensive semiconductor device becomes (1).
実施例の説明
本発明の一実施例を第２図に示す。第１図に示した従来
例とは、チップキャリア２のマザーボード５との接続電
極６を、チップキャリア２の開口部１１１１に形成した
こと、さらに、マザーボード５は、チップキャリア２の
封止蓋としても用いたことが大きく相違する。DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention is shown in FIG. The conventional example shown in FIG. 1 is that the connection electrode 6 of the chip carrier 2 to the motherboard 5 is formed in the opening 1111 of the chip carrier 2, and that the motherboard 5 is used as a sealing lid of the chip carrier 2. The major difference is that they also used
１だ、本発明の半導体装置の製造に際しては、チップキ
ャリア２の中に、半導体チップ１をダイスボンドおよび
ワイヤーボンドした後に、あらかじめ、チップキャリア
の内面に配線形成されたマザーボードとの」妾続電極部
およびその周辺に、スクリーン印刷等で半ＩＢが塗布さ
れたパターンを用いて重ね合わせた後、鉛−錫合金半田
で接続電極６と密封用金属接着部８を、たとえば、温度
１８０°Ｃ程度で同時に加熱、接着させる方法でよい。1. When manufacturing the semiconductor device of the present invention, after the semiconductor chip 1 is dice-bonded and wire-bonded into the chip carrier 2, a "connection electrode" with the motherboard, which has wiring formed on the inner surface of the chip carrier, is formed in advance. After superimposing a pattern in which semi-IB is applied on and around the area by screen printing or the like, the connection electrode 6 and the sealing metal adhesive part 8 are bonded with lead-tin alloy solder at a temperature of about 180°C, for example. A method of heating and bonding at the same time is sufficient.
なお、密封用金属接着部邑は、チップキヤリア内と外気
とを遮蔽させるためである。The purpose of the sealing metal adhesive part is to shield the inside of the chip carrier from the outside air.
発明の効果
以上に述べたように、本発明の半導体装置は、チップキ
ャリアが装着されるマザーボード本来の機能に加えて、
封止蓋としての機能をもたせる結果、従来不可欠とされ
た封止蓋が不要とされること、さらに、従来封止蓋の接
着およびチップギヤリアとマザーボードとの電極間の接
続に用いられた、融点温度の異なる２回の半田処理工程
が１回に低減され、かつ、融点温度の低い、鉛−錫合金
の半田で可能となり、したがって、従来に比して安価な
半導体装置が得られ、その利用価値は大きい０Effects of the Invention As described above, the semiconductor device of the present invention, in addition to the original functions of the motherboard on which the chip carrier is mounted,
As a result of providing the function as a sealing lid, the sealing lid, which was considered indispensable in the past, is no longer necessary, and the melting point temperature that was conventionally used for adhering the sealing lid and connecting the electrodes between the chip gear and the motherboard has been reduced. Two different soldering processes are reduced to one, and it is possible to use lead-tin alloy solder with a low melting point temperature.Therefore, a semiconductor device that is cheaper than conventional ones can be obtained, and its utility value is increased. is a big 0
第１図に１、従来のチップキャリアとマザーボードとの
実装体を示す図、第２図は、本発明の実装体の一実施例
図を示す。
１・・・・・・半導体チップ、２・・・・・・チップキ
ャリア、３・・・・・・高融点半田、４・・・・・・金
属板キャップ、６・・・・・・マザーボード、６・・・
・・・接続電極、７・・・・・・ワイヤー、８・・・・
・・密封用金属接着部。FIG. 1 shows a conventional mounting assembly of a chip carrier and a motherboard, and FIG. 2 shows an embodiment of the mounting assembly of the present invention. 1...Semiconductor chip, 2...Chip carrier, 3...High melting point solder, 4...Metal plate cap, 6...Motherboard , 6...
...Connection electrode, 7...Wire, 8...
・Metal adhesive part for sealing.
Claims (1)
に装着する実装体であって、前記マザーボードは、前記
チップキャリアからの取り出し電極を受ける構造体であ
ると同時に、前記チップキャリアの凹部側を前記マザー
ボー１・に装着することを特徴とする半導体装置。This is a mounting body in which a chip carrier that stores a chip in a recess is attached to a motherboard, and the motherboard is a structure that receives an electrode taken out from the chip carrier, and at the same time, the recess side of the chip carrier is connected to the motherboard 1. A semiconductor device characterized by being attached to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58125304A JPS6017934A (en) | 1983-07-08 | 1983-07-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58125304A JPS6017934A (en) | 1983-07-08 | 1983-07-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6017934A true JPS6017934A (en) | 1985-01-29 |
Family
ID=14906772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58125304A Pending JPS6017934A (en) | 1983-07-08 | 1983-07-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6017934A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62149509A (en) * | 1985-09-17 | 1987-07-03 | Nippon Denso Co Ltd | Cooler for vehicle |
| EP0783183A3 (en) * | 1996-01-05 | 2000-03-29 | Siemens Aktiengesellschaft | Semiconductor device and method of fabrication |
-
1983
- 1983-07-08 JP JP58125304A patent/JPS6017934A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62149509A (en) * | 1985-09-17 | 1987-07-03 | Nippon Denso Co Ltd | Cooler for vehicle |
| EP0783183A3 (en) * | 1996-01-05 | 2000-03-29 | Siemens Aktiengesellschaft | Semiconductor device and method of fabrication |
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