JPS60177714A - Level limiter circuit - Google Patents

Abstract

PURPOSE:To obtain a level compensating function of an output signal for a level limiter circuit by providing a CMOS inverter circuit which works on the level limiter voltage after receiving the inverse signal of an input signal with the output point of said inverse signal connected to an output terminal to the level limiter circuit. CONSTITUTION:A CMOS inverter circuit is provided to prevent the level reduction of an output signal phi' due to a leakage current. This inverter circuit contains a p channel MOSFETQ6 and an n channel MOSFETQ7 which are actuated by the level limiter voltage VcL together with an output terminal connected to an output terminal OUT. While an input terminal of the inverter circuit is connected in common to an input terminal of another CMOS inverter circuit which produces an input signal phi and receives supply of an inverse signal phi''. The FETQ6 is provided with the conductance characteristics of such a small degree that compensates the level reduction due to the leakage current.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a level limiter circuit, and for example, in a CMO3 (complementary MO3) circuit, the level of a signal formed according to a power supply voltage is reduced to an intermediate level below the power supply voltage level. This technology is effective for use in circuits that are limited to

[Background technology]

A circuit as shown in FIG. 1 has been considered as a level limiter circuit that limits a signal formed according to the power supply voltage to an intermediate level below the power supply voltage.

This circuit consists of a transmission gate (MO3FETQI) that transmits an input signal φ formed according to the power supply voltage to the output terminal side, a gate of this MO3FETQI, and a level limiter voltage Vc.
A pair of diode-type MO3FETQ2.
Q3. When the input signal φ is low level, the MO3FETQ2 has the transmission gate MO3FETQ,
Precharge VcL-Vth between the gate and channel of 1. When the input signal φ becomes high level, M
The gate voltage due to self-bootstrap of the transmission gate MO3FETQ1 is set to VcL+Vt by O3FETQ3.
h to set the signal φ° at the output terminal to the level limiter voltage VcL. Note that the above vth is M
This is the threshold voltage of O3FETQI~Q3, and each MO3
The threshold voltages vth of FETQI to Q3 are set to the same value.

In such a level limiter circuit, the node N1 to which the gate of the transmission gate MO3FETQI is connected,
The potential of the node N2, which is the output terminal, decreases over time due to leakage current between the source, drain, and substrate. This has the disadvantage that the output signal φ' decreases over time.

[Purpose of the invention]

An object of the present invention is to provide a novel level limiter circuit having an output signal level compensation function.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a transmission game (MO) that transmits an input signal to an output terminal
A level limiter circuit is provided with a pair of parallel diode-type MOS F'ETs so that current flows in both directions between the gate of the SFET and the level limiter voltage terminal, and an inverted signal of the input signal is received. A CMOS inverter circuit whose output point is connected to the output terminal and is operated by the level limiter voltage is provided to perform level compensation for leakage current.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the level limiter circuit according to the present invention. Each circuit element in the same figure is
It is formed by known CMO3 integrated circuit manufacturing techniques on a semiconductor substrate such as, but not limited to, single crystal silicon.

Although not particularly limited, the input signal φ is formed by a CMOS inverter circuit composed of a P-channel MO5FETQ4 and an N-channel MO3FETQ,5 that operate at the power supply voltage Vcc. Therefore, the input terminal of this CMOS inverter circuit is supplied with an opposite phase signal φ of the input signal φ.

The input signal φ sent from the output terminal of the CMOS inverter circuit is transmitted to the output terminal OUT side through a transmission gate MO3FETQI composed of N-channel MO5FETs. In order to set the level of the output signal φ° sent out from this output terminal OUT to an arbitrary intermediate level below the power supply voltage Vcc, the transmission gate MO3FETQI
A pair of diode-type MOSFETs, Q2. Q3 will be provided.

In this embodiment, the following CMOS inverter circuit is provided as a level compensation circuit for preventing the level of the output signal φ' from decreasing over time due to leakage current. That is, the CMOS is composed of a P-channel MO3FETQ6 and an N-channel MO3FETQ7 that operate based on the level limiter voltage VcL.
An output terminal of the inverter circuit is connected to the output terminal OUT. The input terminal of this CM'OS inverter circuit is commonly connected to the input terminal of the CMOS inverter circuit that forms the input signal φ, and is supplied with the inverted signal φ.

Although not particularly limited, the CMO forming the input signal φ
The P channel MO3FETQ4 of the S inverter circuit is
By setting its conductance characteristic relatively large, it has sufficient driving ability for a load capacitance (not shown) connected through the transmission gate MO3FETQI.

In contrast, N-channel MO3FET Q5 is set to have a small conductance characteristic necessary to reset the small stray capacitance at its output point. On the other hand, P of the CMOS inverter circuit provided for the above level compensation
The channel MO3FETQ6 is set to have a small conductance characteristic that compensates for the level drop due to leakage current, and the N-channel MO3FETQ7 is set to a relatively large conductance characteristic necessary to reset a load capacitance with a relatively large capacitance value. be done.

Next, the operation of the level limiter voltage of this embodiment will be explained according to the operation waveform diagram shown in FIG.

As shown by the broken line in the figure, when the inverted input signal φ is at a high level, the input signal φ is at a low level. Therefore, the N-channel MO3FET Q7 of the CMOS inverter circuit is turned on due to the high level of the inverted input signal φ, so that the output signal φ° is reset to the low level. Also, the gate voltage of the transmission gate MO3FETQI is
Through at least MO3'FETQ2 7 VcL -V
th no L/Hell is precharged. As a result, this MO5FET QI is turned on, and the above level (VcL-Vth) is accumulated in the gate capacitance between its gate and the low level channel.

Next, when the inverted input timing signal 7 changes to low level, the human input signal φ formed by the CMOS impark circuit changes to high level.

At this time, due to the self-bootstrap effect of the transmission gate MO5FETQI, its gate voltage (node Nl)
tries to rise to Vcc+VcL-Vth. However, since the diode type MOSFET Q3 is in the on state and pulls out the boosted voltage to the level limiter voltage VcL side, the level of the node N1 becomes VcL+Vt.
It only rises to h. This allows transmission gate MO3
The level of the output signal φ′ formed through FETQI varies from the gate voltage (VcL+Vth) to the MO3F
This is the voltage (level limiter voltage V cL) obtained by subtracting the threshold voltage Vtl+ of ETQL.

In this embodiment, the input signal φ is at a high level (Vcc
), the conductance characteristic of the P-channel MO5FETQ4 forming the transmission gate IMOS FETQ1 is set to a large value, so that the amount of load g flowing to the output terminal OUT (not shown) via the transmission gate IMOS FETQ1 is quickly charged up. As a result, the output signal φ' increases rapidly up to the limit voltage VcL.

However, over time, the transmission gate MO
Node N1, which is the gate of 3FETQI, and output signal φ
The level of ゛ tends to decrease due to leakage current between the source or drain of the MOSFET and the substrate. In this embodiment, when the output signal φ° is about to decrease due to the leakage current, the P-channel MO5FET, which is turned on by the low level of the inverted input signal φ,
Since current is supplied to compensate for the leakage current through Q6, the level of the output signal ψ° can be maintained at the level limiter voltage VcL.

It is conceivable to form an inverted signal of the input signal and directly perform the above level limiting operation using a CMOS inverter circuit operated by the level limiter voltage VcL, but normally the level limiter voltage VcL is , are formed by dividing the power supply voltage Vcc, etc., so their output impedance becomes large. Therefore, the CM operating with this level limiter voltage VcL
If only the OS inverter circuit is used, the rise of the output signal φ' will be extremely slow and it cannot be put to practical use.

In this regard, in this embodiment, since the output load is driven by a CMOS inverter circuit that generates VJ using the power supply voltage Vcc, the output signal φ rises rapidly.

can be formed.

〔effect〕

(11 Level limiter voltage side MOS
The effect of supplying current through ET is that a stable output signal can be generated regardless of the passage of time.

(By using the 21CM OS circuit, no direct current (through current) is generated between the power supply voltage, level resommiter voltage, and the ground potential point of the circuit, so it is possible to obtain a level limiter circuit with low power consumption. This effect can be obtained.

(3) The N-channel MOS FET on the ground potential side that forms the input signal and the P-channel MOS FET provided for level compensation are formed to have the minimum necessary conductance characteristics. , it is possible to achieve the effect that the cell size can be made smaller.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a CMOS in-hark circuit that forms an input signal is not particularly required as a level limiter circuit. This is because the input signal is formed by some kind of circuit.

[Application field]

The level limiter circuit according to the present invention can be widely used as a level limiter circuit that forms a signal of any intermediate level below the power supply voltage. For example, advances in semiconductor integrated circuit technology have led to miniaturization of elements such as MOSFETs. By miniaturizing this element, MOS F E, T
The withstand voltage tends to decrease. On the other hand, in the development of dynamic RAM with a large storage capacity such as 1M bits, the conventional 64-bit dynamic RAM
In order to be compatible with this, it is necessary to use a high power supply voltage of 5 V for miniaturized elements. In such a case, the level limiter circuit according to the present invention can simply convert the signal level of the WJ.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a level limiter circuit considered prior to the present invention, FIG. 2 is a circuit diagram showing an example of a level limiter circuit according to the present invention, and FIG. is a waveform chart showing an example of the operation. Figure 1 Figure 2 Figure 31￥l

Claims (1)

[Claims] 1. Transmission gate MO3FE that transmits the input signal to the output terminal
A pair of diode-type MOS transistors are provided between the gate of the transmission gate MO3FET and the level limiter voltage terminal, and are arranged in parallel so that current flows in both directions.
A level limiter circuit comprising a FET and a CMOS inverter circuit that receives an inverted signal of the input signal, has an output point connected to the output terminal, and is operated by the level limiter voltage. 2. In the above CMOS inverter circuit, the conductance characteristic of the MOSFET on the level limiter voltage side is set to be small enough to compensate for the leakage current at the output terminal, and the conductance characteristic of the MOSFET on the ground potential side of the circuit is set to be small enough to reset the output level. 2. The level limiter circuit according to claim 1, wherein the level limiter circuit is set to have a necessary driving capability. 3. The above input signal has a large conductance characteristic of the MOS FET on the power supply voltage side, and the MOS FET on the ground potential side has a large conductance characteristic.
The patent is characterized in that it is formed of a CMOS inverter circuit in which the conductance characteristic of T is reduced, and its input terminal is commonly connected to the input terminal of the CMOS inverter circuit that operates at the level limiter voltage. A level limiter circuit according to claim 1 or 2.