JPS60171773A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60171773A
JPS60171773A JP2912984A JP2912984A JPS60171773A JP S60171773 A JPS60171773 A JP S60171773A JP 2912984 A JP2912984 A JP 2912984A JP 2912984 A JP2912984 A JP 2912984A JP S60171773 A JPS60171773 A JP S60171773A
Authority
JP
Japan
Prior art keywords
type
semiconductor substrate
impurities
layer
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2912984A
Other languages
Japanese (ja)
Inventor
Hiroaki Sakamoto
坂本 洋明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Rectifier Corp Japan Ltd
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp Japan Ltd
Infineon Technologies Americas Corp
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp Japan Ltd, Infineon Technologies Americas Corp, International Rectifier Corp USA filed Critical International Rectifier Corp Japan Ltd
Priority to JP2912984A priority Critical patent/JPS60171773A/en
Publication of JPS60171773A publication Critical patent/JPS60171773A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enable to realize the target semiconductor device without passing through a process, wherein a P type diffusion layer formed on the side of eigher of both main surfaces of the semiconductor substrate is removed, by a method wherein N type impurities of high concentration are diffused from the surface of the P type diffusion layer formed on the side of the main surface of the semiconductor substrate and the P type diffusion layer is made to invert into an N type diffusion layer. CONSTITUTION:P type impurities, such as Ga impurities, are thinly diffused from the side of both main surfaces of an N type semiconductor substrate 11 for forming a P type layer 12a and a P type layer 12b. At this time, an SiO2 film 13, with which the whole of the semiconductor substrate 11 is covered, is simultaneously formed by performing a heat oxidation. After the SiO2 film 13 on the side of one main surface of the semiconductor substrate 11, such as the SiO2 film 13 on the side of the P type layer 12a, was removed, N type impurities, such as P impurities of high concentration, are diffused from both main surfaces of the semiconductor substrate 11. In this case, when the P impurities are diffused for a prescribed time, the P type layer 12a is made to invert into an N<+> type layer due to the difference between the diffusion rates in both main surfaces of the semiconductor substrate 11, because the concentration of the P impurities is high. Then, a drive-in heating process is performed, and after that, an N<+> type layer 14' of the target diffusion depth which penetrates the P type layer 12a is obtained. After this, various treatments are performed and the target diode pellet is obtained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法に関し、特に製造工程の
簡略化を図シ製造原価の低減を実現し得る半導体装置の
製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can simplify the manufacturing process and reduce manufacturing costs.

〔発明の技術的時景とその問題点〕[Technical landscape of invention and its problems]

大容量高耐圧用半導体装置、例えばダイオードを製造す
る場合、従来では次のような方法で行なりていた。
When manufacturing a large-capacity, high-voltage semiconductor device, such as a diode, the following method has conventionally been used.

すなわち、第1図は上記製造方法を示す工程図でおって
、まず同装置に示すようにN型半導体基板(1)に対し
てその両生面からP型層(2a)、(2b)を形成すべ
くPfJl不純物、例えばガリウム(Ga)を拡散する
That is, FIG. 1 is a process diagram showing the above manufacturing method, in which first, as shown in the same apparatus, P-type layers (2a) and (2b) are formed on an N-type semiconductor substrate (1) from its ambidextrous surface. Therefore, a PfJl impurity such as gallium (Ga) is diffused.

次に同図(B)に示すように熱酸化法により、二酸化け
い素被膜(SiO□膜)(3)を形成し、次いで同図C
)に示すように前記半導体基板(1)のいずれから一方
の主面側のP型層(2a)、 (2b)のうち、例えば
P型層(2a)を除去する。
Next, as shown in Figure (B), a silicon dioxide film (SiO□ film) (3) is formed by a thermal oxidation method, and then
), for example, among the P-type layers (2a) and (2b) on one main surface side of the semiconductor substrate (1), the P-type layer (2a) is removed.

上記の工程を実施する場合、生産性向上の見地から通常
二枚のウエノ・を互いにラッピングすべき面を外側にし
てワックス等で貼り合せ、それらの板厚を測定して同−
又は近似した板厚を有するグループに分類し、グループ
毎にラッピング機械によりラッピングし前記P型層(2
a)を除去するようにしている。その後、同図0に示す
ようにN+層を形成すべくN型不純物、例えば燐(2)
を拡散する。
When carrying out the above process, from the standpoint of productivity improvement, two sheets of wafer are usually pasted together with wax or the like with the side to be wrapped outward, and the thickness of the sheets is measured.
Alternatively, the P-type layer (2
We are trying to eliminate a). After that, as shown in FIG.
spread.

次いで同図(ト)に示すようにドライブ・イン加熱して
目標の深さのN拡散層(4つを得た後、以下周知の方法
にしたがって各種の処理を施こし目標とするダイオード
ベレットを得る。
Next, as shown in the same figure (G), drive-in heating is performed to obtain N diffusion layers (4) of the target depth, and then various treatments are performed according to well-known methods to form the target diode pellet. obtain.

しかるに上記の製造方法では特に−主面側のP型層(2
a)を除去する工程が複雑でかつ長時間要しそのため製
品原価の高騰の一因となっていた。
However, in the above manufacturing method, the P-type layer (2
The process of removing a) is complicated and takes a long time, which is one of the reasons for the rise in product costs.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に基づきなされたもので、半導体基
板の一生面側のP型層を除去する工程を経ることなく目
標とする半導体装置を得られるようにした半導体装置の
製造方法を提供することを目的とする。
The present invention has been made based on the above-mentioned circumstances, and provides a method for manufacturing a semiconductor device that allows a target semiconductor device to be obtained without going through the step of removing the P-type layer on the entire surface side of a semiconductor substrate. The purpose is to

〔発明の概要〕[Summary of the invention]

本発明は半導体基板に形成したいずれか一方の主面側の
P型拡散層をラッピング等で除去することなく、そのP
型拡散層上から菌濃度N型不純物を拡散させ、N型拡散
層に反転させることにより製造工程を簡略化し、製造原
価の低減を図った半導体装置の製造方法である。
The present invention enables the P-type diffusion layer formed on one of the main surfaces of the semiconductor substrate to be removed without removing it by lapping or the like.
This method of manufacturing a semiconductor device simplifies the manufacturing process and reduces manufacturing costs by diffusing N-type impurities with a bacterial concentration from above the type diffusion layer and inverting it to the N-type diffusion layer.

〔発明の実施例〕[Embodiments of the invention]

以下に本発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の半導体装置の製造方法を示す工程図で
ある。
FIG. 2 is a process diagram showing a method of manufacturing a semiconductor device according to the present invention.

まず、同装置に示すようにN型半導体基板(11)の両
生面側からP型層(12a)、(12b)を形成すべく
P型不純物、例えばGaを薄く、例えば深さ約10μm
程度拡散する。この時のGaの不純物濃度は約1016
〜1019atoms/cJである。
First, as shown in the same apparatus, in order to form P-type layers (12a) and (12b) from the bidirectional side of an N-type semiconductor substrate (11), a P-type impurity, for example, Ga is applied thinly, for example, to a depth of about 10 μm.
Diffuse to some extent. The impurity concentration of Ga at this time is approximately 1016
~1019 atoms/cJ.

尚、この時、同時に熱酸化によシ半導体基板(11)の
全体を覆う5i02膜(13)が形成される。
At this time, a 5i02 film (13) covering the entire semiconductor substrate (11) is simultaneously formed by thermal oxidation.

次に同図(B)に示すように半導体基板(11)の−主
面側、例えば前記P型層(12a)側の5i02膜(1
3)を公知の方法によって除去する。
Next, as shown in the same figure (B), the 5i02 film (1
3) is removed by a known method.

さらに同図(C)に示すように5i02膜(13)を除
去した側のP型層を反転させてN型層を形成すべくN型
不純物、例えばP (IJン)を拡散する。この場合、
Pの不純物濃度は約1019〜10” atoms/C
4程度で前記P型層(12)を形成したGaの不純物濃
度的1O16〜1019atoms/c111に比し十
分不純物濃度が高いために所定時間拡散すると、両者の
拡散速度の相違によりp型層(12a)を1層(14)
に反転させる。その後、同図(ハ)のドライブ・イン加
熱工程を経でP型層(12g)をつき抜けて目標の拡散
深さのN+層(14’)を得る。
Further, as shown in FIG. 2C, the P-type layer on the side from which the 5i02 film (13) has been removed is inverted and an N-type impurity, for example, P (IJn), is diffused to form an N-type layer. in this case,
The impurity concentration of P is approximately 1019 to 10” atoms/C
Since the impurity concentration of Ga used to form the P-type layer (12) is sufficiently high compared to 1016 to 1019 atoms/c111, when the p-type layer (12a) is diffused for a predetermined time, the p-type layer (12a ) in one layer (14)
invert it. Thereafter, through the drive-in heating process shown in FIG. 3(C), the P-type layer (12g) is penetrated to obtain the N+ layer (14') having the target diffusion depth.

以下は従来と同様に公知の処理工程を経て目標とするダ
イオードペレッ)f4’Jる。
Hereafter, the target diode pellet (f4'J) is produced through known processing steps in the same manner as in the prior art.

〔発明の効果〕〔Effect of the invention〕

本発明は上記のように半導体基板の一生面側のP型層を
ラッピング機械等によって除去することなく、反対4電
型のN型不純物の拡散によシP型層全面をN型層に反転
させるようにしたので複雑かつ長時間要する上記除去工
程を不要とし半導体装置の製造工程の簡略化にょシ著し
く製造原価を低減することができる。
As described above, the present invention does not require removing the P-type layer on the surface side of the semiconductor substrate using a lapping machine or the like, but instead converts the entire P-type layer into an N-type layer by diffusing N-type impurities of the opposite 4-voltage type. This eliminates the need for the complicated and time-consuming removal step, which simplifies the manufacturing process of semiconductor devices and significantly reduces manufacturing costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第11!n(A)乃至(ト)は従来の半導体装置の製造
方法の一例を示す工程図、第2図(4)乃至0は本発明
に係る半導体装置の製造方法の一実施例を示す工程図で
ある。 11・・・N型半導体基板、 12a112b −P型層、 13・・・SiO□膜 14.14’・・・N型層。 出願人 日本インターナショナル整等1整株式会社第1
図 第2図
11th! n(A) to (G) are process diagrams showing an example of a conventional method for manufacturing a semiconductor device, and FIGS. 2(4) to 0 are process diagrams showing an example of a method for manufacturing a semiconductor device according to the present invention. be. 11...N-type semiconductor substrate, 12a112b-P-type layer, 13...SiO□ film 14.14'...N-type layer. Applicant: Japan International Seiichi Co., Ltd. No. 1
Figure 2

Claims (1)

【特許請求の範囲】 N型半導体基板の両生面からP型不純物を拡散して両生
面側にP型層を形成する工程と、上記P型層のうち、い
ずれか一方のP型層上からこのP襠 型層つき抜けてN型に反転させるのに十分な不純物濃度
を有する高濃度N型不純物を拡散する工程とを有するこ
とを特徴とする半導体装置の製造方法。
[Claims] A step of diffusing P-type impurities from both sides of an N-type semiconductor substrate to form a P-type layer on the side of the both sides, and a step of forming a P-type layer on one of the above-mentioned P-type layers. A method for manufacturing a semiconductor device, comprising the step of diffusing a high concentration N-type impurity having a sufficient impurity concentration to penetrate through this P-type layer and invert it to an N-type.
JP2912984A 1984-02-17 1984-02-17 Manufacture of semiconductor device Pending JPS60171773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2912984A JPS60171773A (en) 1984-02-17 1984-02-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2912984A JPS60171773A (en) 1984-02-17 1984-02-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60171773A true JPS60171773A (en) 1985-09-05

Family

ID=12267684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2912984A Pending JPS60171773A (en) 1984-02-17 1984-02-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60171773A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56946A (en) * 1979-06-15 1981-01-08 Sanyo Electric Co Ltd Warm-air heater

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56946A (en) * 1979-06-15 1981-01-08 Sanyo Electric Co Ltd Warm-air heater

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