JPS60161669A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60161669A JPS60161669A JP59015213A JP1521384A JPS60161669A JP S60161669 A JPS60161669 A JP S60161669A JP 59015213 A JP59015213 A JP 59015213A JP 1521384 A JP1521384 A JP 1521384A JP S60161669 A JPS60161669 A JP S60161669A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor device
- film
- offset
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 8
- 230000010354 integration Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000004904 shortening Methods 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 229910005091 Si3N Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000901143 Etia Species 0.000 description 1
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は高速作動を可能とし、かつ一方では高集積化や
耐圧の向上を可能にした半導体装置およびその製造方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device that enables high-speed operation, high integration, and improved breakdown voltage, and a method for manufacturing the same.
近年のＩＣ，ＬＳＩ等の半導体装置は益々高集積化が図
られており、ＭＯＳＦＥＴ（ＭＯ８型電界効果トランジ
スタ）では短チヤネル化が図られている。しかしながら
、短チヤネル化を進めると、いわゆる短チヤネル効果で
生じるしきい値のゲート長依存性などの副作用を防ぐ上
からソース・ドレイン領域を浅くしなければならず、こ
れらソース・ドレイン領域の抵抗が犬となって素子の高
速化の障害になる。また、短チヤネル化に伴なって耐圧
にも問題が生じることとなり、従来、ソース・ドレイン
領域を高濃度の領域主部と、低濃度の領域とからなるプ
ロファイルのＬｉｇｈｔｌｙ ＤｏｐｅｄＤｒａｉｎ
構造が提案されてきている（ＩＥＥＥＴＲＡＮＳＡＣＴ
ＩＯＮＳ ＯＮ ＥＬＥＣＴＲＯＮＤＥＶＩＣＥＳ、Ｖ
ＯＬ ＥＤ−２９，Ｎｏ、４ＡＰＲＩＬ１９８２ Ｐ５
９０〜）。しかし、抵抗が相対的に小さい領域主部が更
に微小化されてしまい、前述した高抵抗化を助長するこ
とになる。また、ソース・ドレイン領域の特に高濃度部
位が直接逆導電型の基板やウェルに接している構成であ
ることから、接合容量が太き（１よると共に、これをＣ
−ＭＯ８構造に用いたときにはランチアンプ耐圧が低く
なり、素子分離寸法を大きくしなげればならない等高集
積化の障害となる。In recent years, semiconductor devices such as ICs and LSIs have become increasingly highly integrated, and MOSFETs (MO8 field effect transistors) have been made to have shorter channels. However, as channels become shorter, the source and drain regions must be made shallower in order to prevent side effects such as gate length dependence of the threshold value caused by the so-called short channel effect, and the resistance of these source and drain regions increases. It becomes a dog and becomes an obstacle to increasing the speed of the element. In addition, with the shortening of channels, problems arise with breakdown voltage. Conventionally, the source/drain regions have a profile consisting of a main part of a highly doped region and a lightly doped region.
Structures have been proposed (IEEE
IONS ON ELECTRON DEVICE,V
OL ED-29, No, 4APRIL1982 P5
90~). However, the main portion of the region with relatively low resistance is further miniaturized, which promotes the above-mentioned increase in resistance. In addition, since the particularly high concentration portions of the source/drain regions are in direct contact with the opposite conductivity type substrate or well, the junction capacitance is large (1) and this
- When used in the MO8 structure, the launch amplifier breakdown voltage becomes low, which becomes an obstacle to high-density integration, which requires increasing element isolation dimensions.
本発明の目的は短チヤネル化を図ったＭＯＳＦＥＴのソ
ース・ドレイン領域の低抵抗化を図って高速化を可能に
すると共に、その耐圧の向上および接合容量の低減を可
能とし、更に高集積化を達成することのできる半導体装
置を提供することにある。The purpose of the present invention is to reduce the resistance of the source/drain regions of a MOSFET with a short channel, thereby making it possible to increase the speed of the MOSFET, as well as to improve its breakdown voltage and reduce its junction capacitance. The object of the present invention is to provide a semiconductor device that can achieve the above goals.
また、本発明の他の目的は前記した高速作動可能でかつ
高集積化を達成する半導体装置の好適な製造方法を提供
することにある。Another object of the present invention is to provide a suitable method for manufacturing the semiconductor device described above, which is capable of high-speed operation and achieves high integration.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細省の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、オフセット構造に形成したＭＯＳＦＥＴのソ
ース・ドレイン領域における領域主部を深く形成すると
共に、この領域主部と基板側との界面に絶縁膜を介在さ
せる構成とすることにより、耐圧の向上はもとよりソー
ス・ドレイン領域の見かけ上の深さを大きくして低抵抗
化、つまり高速化を達成し、更に接合容量の低減を図り
、しかも短チヤネル化により高集積化を達成するもので
ある。That is, by forming the main part of the source/drain region of a MOSFET formed in an offset structure deeply, and by interposing an insulating film at the interface between the main part of this region and the substrate side, not only the breakdown voltage can be improved. The apparent depth of the source/drain regions is increased to achieve lower resistance, that is, higher speed, and furthermore, junction capacitance is reduced, and moreover, high integration is achieved by shortening the channels.
また、ソース・ドレイン領域のオフセット部位を形成し
た後に領域主部の部位に溝を形成し、この溝の表面に絶
縁膜を形成した上で溝内に導電材料を充填することによ
り、前記高速作動型、高集積型の半導体装置の製造を完
成するものである。Furthermore, after forming the offset portions of the source/drain regions, a groove is formed in the main portion of the region, an insulating film is formed on the surface of the groove, and a conductive material is filled in the groove. This completes the manufacturing of highly integrated semiconductor devices.
第１図は本発明の半導体装置をＮ型ＭＯ８ＦＥＴ１に適
用した実施例を示している。即ち、Ｐ型のシリコン半導
体基板２の主面上には選択酸化法（ＬＯＣＯ８法）で形
成したフィールド絶縁膜３を設けて活性領域を画成し、
この活性領域内にＮ−ＭＯ８ＦＥＴＩを構成している。FIG. 1 shows an embodiment in which the semiconductor device of the present invention is applied to an N-type MO8FET1. That is, a field insulating film 3 formed by a selective oxidation method (LOCO8 method) is provided on the main surface of a P-type silicon semiconductor substrate 2 to define an active region.
An N-MO8FETI is configured within this active region.
このＮ−ＭＯ８ＦＥＴＩはゲート絶縁膜４上に形成した
ゲート電ｒｉ、５と、Ｎ型不純物をドープさせたソース
・ドレイン領域６．６とで構成しており、特にソース・
ドレイン領域は不純物濃度の低い（Ｎ−）部分７．７と
、これらの各外側に連続する不純物濃度の高い（Ｎ＋）
領域主部８．８とで形成している。そして、前記領域主
部８．８は基板２の内方に向がって深く形成して低抵抗
化を図っている。ｆだ、領域主部８．８と基板２との界
面にはシリコン酸化膜（ＳｊＯ，膜）かもなる絶縁膜９
．９を形成し、各領域主部８．８における接合容量の低
減を図っている。図中、ｉｏ、ｉｉはＳｉｎ、、ＰＳＧ
の層間絶縁膜１２．１２はＡｎ配線である。This N-MO8FETI is composed of a gate voltage ri, 5 formed on a gate insulating film 4, and source/drain regions 6.6 doped with N-type impurities.
The drain region has a low impurity concentration (N-) part 7.7 and a continuous high impurity concentration (N+) part 7.7 on the outside of each of these parts.
It is formed by a main area 8.8. The main region portion 8.8 is formed deeply inward of the substrate 2 to lower the resistance. f, at the interface between the main region 8.8 and the substrate 2, there is an insulating film 9 which may also be a silicon oxide film (SjO, film).
．． 9 is formed to reduce the junction capacitance in each region main portion 8.8. In the figure, io and ii are Sin, PSG
The interlayer insulating film 12.12 is an An wiring.
次に以上の構成のＮ−ＭＯ８ＦＥＴＩの製造方法を第２
図囚〜（Ｉ＋の工程図に基づいて説明する。Next, a second method for manufacturing the N-MO8FETI with the above configuration will be described.
The explanation will be based on the process diagram of I+.
先ず、第２図（３）のようにＰ型シリコン基板２の主面
にＬＯＣＯ８法によりフィールド絶縁膜（ＳｉＯ，）３
を形成して活性領域な画成すると共に、この活性領域上
にゲート絶縁膜（ＳｉＯ２）４を形成し、更にその上に
ポリシリコン層を形成した上でこれをバターニングして
ゲート電極５を形成する。しかる後に不純物としてりん
Ｐ）を自己整合によって基板主面にドープさせ、オフセ
ット部７．７に相当する低濃度のＮ一層７ａ、７ａを形
成する。First, as shown in FIG. 2(3), a field insulating film (SiO,) 3 is formed on the main surface of a P-type silicon substrate 2 by the LOCO8 method.
A gate insulating film (SiO2) 4 is formed on this active region, and a polysilicon layer is further formed on it, and this is buttered to form a gate electrode 5. Form. Thereafter, the main surface of the substrate is doped with phosphorus (P) as an impurity by self-alignment to form a low concentration N layer 7a, 7a corresponding to the offset portion 7.7.
次いで、同図刊のようにシリコンナイトライド膜（Ｓｉ
、Ｎ４）１３およびＳｉＯ□膜１４をＣＶＤ法により全
面に形成し、その後これを反応性イオンエツチング法（
ＲＩＥ）によりエツチング除去することにより、同図（
Ｃ１のようにゲート電極５０両側にサイドウオール１５
．１５を形成する。このとき、５ｉｎ２膜１４を比較的
厚く形成しておけば、ゲート電極５における断面形状と
ＲＩＥ法の関係により、ゲート電極５上にもＳ ｉ０２
膜１４とＳｉ、Ｎ４膜１３を若干残すことができる。そ
して、このサイドウオール１５．１５をマスクとしてソ
ース・ドレイン領域６．６に前記Ｎ一層７ａ。Next, as shown in the same publication, a silicon nitride film (Si
, N4) 13 and SiO
The same figure (
Sidewalls 15 are placed on both sides of the gate electrode 50 as shown in C1.
．． form 15. At this time, if the 5in2 film 14 is formed relatively thick, Si02 will also be formed on the gate electrode 5 due to the relationship between the cross-sectional shape of the gate electrode 5 and the RIE method.
The film 14 and the Si, N4 film 13 can be left slightly. Then, using this sidewall 15.15 as a mask, the N layer 7a is applied to the source/drain region 6.6.
７ａと同じ深さの溝１６．１６をエツチング形成する。A groove 16.16 of the same depth as 7a is etched.
次に、再びＳ ｉ ３Ｎ４膜（第２Ｓｉ３・Ｎ４膜）１
７とＳ ｉ０２膜（第２ＳｉＯ３膜）１８をＣＶＤ法に
より全面に形成し、かつこれをＲＩＥ法によりエツチン
グ処理することにより、同図の）のように前記サイドウ
オール１５．１５の両側ないし前記溝１６．１６の内立
面に第２サイドウオール１９．１９を形成する。そして
、再びこの第２サイドウオール１９．１９をマスクとし
そ基板２をエツチングし、前記溝１６．１６の下側に同
図田）のように、更に深い新たな溝２０．２０を形成す
る。Next, Si 3N4 film (second Si3/N4 film) 1
7 and a SiO2 film (second SiO3 film) 18 are formed on the entire surface by CVD method, and etched by RIE method, thereby forming both sides of the sidewall 15, 15 or the groove. A second sidewall 19.19 is formed on the inner vertical surface of 16.16. Then, using the second sidewall 19.19 as a mask, the substrate 2 is etched again to form a new, deeper groove 20.20 below the groove 16.16 as shown in the same figure.
次いで、同図（Ｆ′）のように、第２８ｉＯ２膜１８を
エツチング除去した上で溝２０．２０内面を酸化して酸
化膜９．９を絶縁膜として形成する。このとき、領域７
．７の側面は第２Ｓｉ３Ｎ、膜１７．１７に被覆されて
いるので酸化膜が形成されることはない。しかる上で、
第２Ｓｉ３Ｎ、膜１７を除去した後、同図（０のように
高濃度にＮ型不純物をドープしたポリシリコン８ａを全
面に堆積させる。このとき、溝２０．２０はポリシリコ
ン８ａにより充填される。そして、このポリシリコン８
ａを表面からエツチングバックすれば、前記溝２０．２
０内のポリシリコン８ａのみが残され、同図σ」のよう
に高濃度不純物（Ｎ″−）の領域主部８．８が構成され
る。この領域主部８．８は低濃度不純物の前記オフセッ
ト部７．７と接続状態にあり、これにより各領域主部８
．８と領域７．７とでソース・ドレイン領域６．６を形
成する。Next, as shown in FIG. 2F, the 28th iO2 film 18 is removed by etching, and the inner surface of the groove 20.20 is oxidized to form an oxide film 9.9 as an insulating film. At this time, area 7
．． Since the side surfaces of 7 are covered with the second Si3N film 17.17, no oxide film is formed. However,
After removing the second Si3N film 17, polysilicon 8a doped with N-type impurities at a high concentration is deposited on the entire surface as shown in the same figure (0).At this time, the trenches 20 and 20 are filled with polysilicon 8a. .And this polysilicon 8
If a is etched back from the surface, the grooves 20.2
Only the polysilicon 8a within 0 is left, forming a main region 8.8 of high concentration impurity (N"-) as shown in the figure σ". The offset portion 7.7 is connected to the main portion 8 of each area.
．． 8 and the region 7.7 form a source/drain region 6.6.
しかる上で、ゲート電極５の５ｉ０２１１ｕ１４とＳＬ
、Ｎ４膜１３を除去し、改めて酸化処理して同図ｆＩ）
のよ５にゲート電極５ないしソース・ドレイン領域６．
６上にＳ ｉｏ ２膜」０を形成する。更にその上にＰ
ＳＧ膜１１を形成し、かつコンタクトホールの形成後に
Ａｌ配線１２．１２を形成すれば第１図のＮ−ＭＯ８Ｆ
ＥＴＩを完成することができる。In addition, 5i0211u14 of gate electrode 5 and SL
, the N4 film 13 is removed and oxidized again (FIG. fI).
Gate electrode 5 or source/drain region 6.
6, an S io 2 film 0 is formed on top of the 6. Furthermore, P on top of that
If the SG film 11 is formed and the Al wiring 12.12 is formed after the contact hole is formed, the N-MO8F shown in FIG.
Able to complete ETI.
以上のように形成されたＮ−ＭＯ８ＦＥＴＩによれば、
ソース・ドレイン領域６．６は不純物濃度の低い領域７
．７と、濃度の高い領域主部８．８とで形成され、かつ
ゲート電極５とで構成されていることになる。したがっ
て、短チヤネル化した場合にもその耐圧を高いものにで
きる。一方、ソース・ドレイン領域６．６のこの構造に
より、領域の広い部分を占める領域主部８．８の深さを
大きくできるのでその低抵抗化を図り、高速化を実現で
きる。この場合、領域７．７は従来通りであり、短チヤ
ネル化に伴なうしきい値のゲート長依存性の副作用が生
じることはない。更に、領域主部８．８と基板２との界
面には絶縁膜９．９を形成しているので、ソース・ドレ
イン領域６．６全体の接合容量を大幅に低減することも
できる。According to the N-MO8FETI formed as described above,
Source/drain regions 6.6 are regions 7 with low impurity concentration
．． 7, a high concentration region main portion 8.8, and the gate electrode 5. Therefore, even when the channel is shortened, the withstand voltage can be increased. On the other hand, this structure of the source/drain region 6.6 allows the depth of the main region 8.8, which occupies a wide portion of the region, to be increased, thereby lowering the resistance and realizing higher speed. In this case, the region 7.7 is the same as before, and the side effect of the gate length dependence of the threshold value due to the shortening of the channel does not occur. Furthermore, since the insulating film 9.9 is formed at the interface between the main region 8.8 and the substrate 2, the junction capacitance of the entire source/drain region 6.6 can be significantly reduced.
結局、短チヤネル化に伴なつ拙々の不具合を防止でき、
集子の微細化を図って高集積化を達成できる。In the end, it is possible to prevent the awkward problems associated with shortening the channel.
High integration can be achieved by miniaturizing the cluster.
ここで、領域主部８．８の絶縁膜９．９は素子間分離用
の絶縁膜として利用することもでき、したがって第３図
のように２個のＭＯ８ＦＥＴＩＡ。Here, the insulating film 9.9 in the main region 8.8 can also be used as an insulating film for isolation between elements, and therefore two MO8FETIAs are used as shown in FIG.
ＩＢを近接して配置することもできる８この構造を同図
のように、Ｐウェル２］、Ｎウェル２２上に形成したＮ
−ＭＯＳ Ｆ、Ｅ Ｔ Ｉ Ａ、 Ｐ−ＭＯＳ ＦＥＴ
ＩＢからなるｃ−Ｍｏｓデバイスに適用した場合には、
高集積化、高速度化に加えてラッチアップ耐圧の向上も
可能とされる。第３図中、第１図に対応する部分には同
一符号を付しである。The IBs can be placed close to each other.8 This structure can be used as shown in the same figure for the N well 2 formed on the
-MOS FET, ETIA, P-MOS FET
When applied to a c-Mos device consisting of IB,
In addition to higher integration and speed, it is also possible to improve latch-up resistance. In FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals.
（１１ＭＯＳＦＥＴのソース・ドレイン領域を低不細物
濃度領域と領域主部とからなるオフセット構造としてい
るので、耐圧の向上を図ることができる。(Since the source/drain regions of the MOSFET 11 have an offset structure consisting of a low impurity concentration region and a main region, the breakdown voltage can be improved.
（２） ソース・ドレイン領域の領域主部のみを深く形
成しているので、短チヤネル化に伴なうしきい値のゲー
ト長依存性の副作用を防止する一方で、ソース・ドレイ
ン領域の低抵抗化を達成でき、高速化を達成できる。(2) Only the main part of the source/drain region is formed deeply, which prevents the side effects of gate length dependence of the threshold value due to shorter channels, while reducing the resistance of the source/drain region. can be achieved and high speed can be achieved.
（３）領域主部と基板との界面に絶縁膜を形成している
ので、接合容量の低減を図ることができ、高速化を助長
すると共に動作の安定化を図ることができる。(3) Since an insulating film is formed at the interface between the main region and the substrate, it is possible to reduce the junction capacitance, thereby promoting high speed operation and stabilizing the operation.
（４）短チヤネル化によっても耐圧の向上、高速化等を
達成できるので、素子の微細化を進めて高集積化を達成
できる。(4) By shortening the channels, it is possible to improve breakdown voltage and increase speed, so it is possible to advance the miniaturization of elements and achieve high integration.
（５）ゲート電極の自己整合を利用したエツチング技術
により溝を形成し、溝内面の酸化技術により絶縁膜を形
成し、かつポリシリコンの堆積、エツチングバンク技術
によりソース・ドレインの領域主部を形成できので、特
殊な技術を必要とすることなく、しかも従来のＭＯＳＦ
ＥＴの製造工程に比べて大幅に工程数を増加することな
く高耐圧、高速、高集積度の半導体装置を製造すること
ができる。(5) Form a trench using etching technology that utilizes self-alignment of the gate electrode, form an insulating film using oxidation technology on the inner surface of the trench, and form the main part of the source/drain region using polysilicon deposition and etching bank technology. Therefore, it does not require any special technology and can be done using conventional MOSFETs.
A semiconductor device with high breakdown voltage, high speed, and high integration can be manufactured without significantly increasing the number of steps compared to the ET manufacturing process.
以上本発明者によってなされた発明を実施例に −もと
づき具体的に説明したが、本発明は上記実施例に限定さ
れるものではなく、その要旨を逸脱しない範囲で種々変
更可能であることはいうまでもない。たとえば、ソース
・ドレイン領域の領域主部を高濃度不純物ポリシリコン
に代えて金属又は金属シリサイドを使用してもよく、低
抵抗化を一層向上することができる。また、溝の形成に
はホトリソグラフィ技術を利用した選択エツチング法を
利用してもよい。更に、各膜の形成法やポリシリコンの
堆積法にはＣＶＤ法の外種々の方法が利用できる。The invention made by the present inventor has been specifically explained above based on Examples, but it should be noted that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Not even. For example, metal or metal silicide may be used instead of heavily doped polysilicon for the main portions of the source/drain regions, and the resistance can be further reduced. Alternatively, a selective etching method using photolithography may be used to form the grooves. Furthermore, various methods other than the CVD method can be used for forming each film and depositing polysilicon.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である基本ＭＯ，’Ｓ Ｆ
Ｅ Ｔに適用した場合につし・て説明したが、それに
限定されるものではな（このＭＯＳＦＥＴを素子とする
ＩＣ，ＬＳＩの全てに適用することができ、特に高速、
高集積型の半導体装置に有効に適用できる。In the above explanation, the invention made by the present inventor will be mainly explained in terms of the basic MO, 'S F
Although the explanation has been made for the case where it is applied to ET, it is not limited thereto (it can be applied to all ICs and LSIs that use this MOSFET as an element, especially for high-speed,
It can be effectively applied to highly integrated semiconductor devices.
第１図は本発明の一実施例の断面図、
第２回込）〜（Ｉｌは製造工程の断面図、第３図は変形
例の断面図である。
１、ＩＡ、ＩＢ・・・ＭＯ８Ｆ’ＥＴ１２・・・半導体
基板、３・・・フィールド絶縁膜、４・・・ゲート絶縁
膜、５・・・ゲート電極、６・・・ソース・ドレイン領
域、７・・・低不純物濃度領域、８・・・領域主部、９
・・・絶縁膜、１０・・・５ｉｎ２膜、１１・・・ＰＳ
Ｇ膜、１５・・・サイドウオール、１６・・・溝、１９
・・・第２サイドウオール、２０・・・溝、２１・・・
Ｐウェル、２２・・・Ｎウェル。
代理人 弁理士 高 橋 明 失
策 １ 図
第 ３ 図
第 ２ 図
どＡ）
（Ｂ）
第 ２ 図Fig. 1 is a sectional view of an embodiment of the present invention, 2nd round) - (Il is a sectional view of the manufacturing process, and Fig. 3 is a sectional view of a modified example. 1, IA, IB...MO8F 'ET12... Semiconductor substrate, 3... Field insulating film, 4... Gate insulating film, 5... Gate electrode, 6... Source/drain region, 7... Low impurity concentration region, 8 ...Region main part, 9
...Insulating film, 10...5in2 film, 11...PS
G film, 15... Side wall, 16... Groove, 19
...Second side wall, 20...Groove, 21...
P well, 22...N well. Agent Patent Attorney Akira Takahashi Mistake 1 Figure 3 Figure 2 Figure A) (B) Figure 2
Claims (1)
領域を、低不純物濃度のオフセット部と、その外側に連
なる領域主部とで構成し、この領域主部はオフセット部
よりも深く形成すると共に基板側との界面に絶縁膜を介
在させたことを特徴とする半導体装置。 ２、領域主部を高不純物濃度の半導体材料で形成してな
る特許請求の範囲第１項記載の半導体装置。 ３、領域主部を金属又は金属シリサイドで形成してなる
特許請求の範囲第１項記載の半導体装置。 ４、ＭＯＳＦＥＴのソース・ドレイン領域の形成に際し
、先に低不純物濃度のオフセット部を形成し、その後領
域主部に相当する部位の半導体基板にオフセット部より
も深い溝を形成し、この溝の内面に絶縁膜を形成した上
で溝内に低抵抗材料を充填して領域主部を構成したこと
を特徴とする半導体装置の製造方法。 ５、オフセット部をゲートを極を利用した自己整合法に
より形成し、その後ゲート電極にサイドウオールを形成
しかつこれをマスクとして領域主部の溝をエツチング形
成してなる特許請求の範囲第４項記載の半導体装置の製
造方法。 ６、溝内面を酸化して酸化膜を形成し、この酸化膜を絶
縁膜として形成してなる特許請求の範囲第４項又は第５
項記載の半導体装置の製造方法。[Claims] 1. The source 0 drain region of a MOSFET with an offset structure is composed of an offset part with a low impurity concentration and a main part of the region continuous to the outside thereof, and the main part of the region is formed deeper than the offset part. A semiconductor device characterized in that, at the same time, an insulating film is interposed at the interface with the substrate side. 2. The semiconductor device according to claim 1, wherein the main region is formed of a semiconductor material with a high impurity concentration. 3. The semiconductor device according to claim 1, wherein the main region is formed of metal or metal silicide. 4. When forming the source/drain regions of a MOSFET, first form an offset part with a low impurity concentration, then form a trench deeper than the offset part in the semiconductor substrate at a portion corresponding to the main part of the region, and then 1. A method of manufacturing a semiconductor device, characterized in that a main region is formed by forming an insulating film on the substrate and then filling a trench with a low-resistance material. 5. Claim 4, in which the offset portion is formed by a self-alignment method using a gate electrode, and then a sidewall is formed on the gate electrode, and a groove in the main region is etched using this as a mask. A method of manufacturing the semiconductor device described above. 6. The inner surface of the groove is oxidized to form an oxide film, and this oxide film is formed as an insulating film as claimed in claim 4 or 5.
A method for manufacturing a semiconductor device according to section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59015213A JPH067596B2 (en) | 1984-02-01 | 1984-02-01 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59015213A JPH067596B2 (en) | 1984-02-01 | 1984-02-01 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60161669A true JPS60161669A (en) | 1985-08-23 |
| JPH067596B2 JPH067596B2 (en) | 1994-01-26 |
Family
ID=11882592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59015213A Expired - Lifetime JPH067596B2 (en) | 1984-02-01 | 1984-02-01 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067596B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63147359A (en) * | 1986-08-11 | 1988-06-20 | テキサス インスツルメンツ インコーポレイテツド | Semiconductor integrated circuit and manufacture of the same |
| WO1999025025A1 (en) * | 1997-11-07 | 1999-05-20 | Siemens Aktiengesellschaft | Mos transistor and process for producing the same |
| US7528453B2 (en) * | 2002-10-07 | 2009-05-05 | Infineon Technologies Ag | Field effect transistor with local source/drain insulation and associated method of production |
| CN103426753A (en) * | 2012-05-14 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for source drain region and metal oxide semiconductor (MOS) device |
-
1984
- 1984-02-01 JP JP59015213A patent/JPH067596B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63147359A (en) * | 1986-08-11 | 1988-06-20 | テキサス インスツルメンツ インコーポレイテツド | Semiconductor integrated circuit and manufacture of the same |
| WO1999025025A1 (en) * | 1997-11-07 | 1999-05-20 | Siemens Aktiengesellschaft | Mos transistor and process for producing the same |
| US7528453B2 (en) * | 2002-10-07 | 2009-05-05 | Infineon Technologies Ag | Field effect transistor with local source/drain insulation and associated method of production |
| US7824993B2 (en) * | 2002-10-07 | 2010-11-02 | Infineon Technologies Ag | Field-effect transistor with local source/drain insulation and associated method of production |
| US9240462B2 (en) | 2002-10-07 | 2016-01-19 | Infineon Technologies Ag | Field-effect transistor with local source/drain insulation and associated method of production |
| CN103426753A (en) * | 2012-05-14 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for source drain region and metal oxide semiconductor (MOS) device |
| CN103426753B (en) * | 2012-05-14 | 2016-06-22 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of source-drain area and MOS device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH067596B2 (en) | 1994-01-26 |
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