JPS60159934A - Decimal code adding circuit - Google Patents

Abstract

PURPOSE:To obtain a decimal code adding circuit which does not require a position matching circuit for adding a code, by constituting so that the code can be added to an optional position of a processing object data. CONSTITUTION:An input data line 10 leads a processing object data DI, and inputs it to a selecting circuit 20. A selector 21 becomes an output permitted state when an E input is low, and becomes an output high impedance when said input is high. A selector 22 is always in an output permitted state. A control signal ZONE for showing whether a data format of a data to be processed is a pack format or a zone format is supplied to a terminal E of the selector 21. Also, code adding position information SP of 2 bit is supplied to a terminal S of the selectors 21, 22. The information SP is supplied from a code adding position determining circuit 30, and indicates which byte part of the data DI on the input data line 10 the code adding position becomes, that is to say, which of DI0-DI3 it becomes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a decimal code adding circuit suitable for a data processing device to which packed format and zone format decimal data are applied.

[Technical background of the invention and its problems]

There are two formats for representing decimal numbers: pack format and scene format. In the /gutsuku format, one digit of a one-digit decimal number is expressed in four bits, so one byte can represent two digits as shown in the first column.
A 0-decimal number is represented.

Further, the code S is represented by the lower 4 bits of the least significant byte. S=+C indicates positive, S=suD indicates negative.

Note that symbols indicate hexadecimal representation. On the other hand, in the zone format, one decimal digit is expressed in one byte. There are four zone formats as shown in FIGS. 2(a) to 2(d). FIG. 2(,) shows a code-mixed type in which the code is placed after the code, and FIG. 2(b) similarly shows a code-separated type. Also, the second
Figure (C) shows the code mixed type of code prefix, and Figure 2 (d)
) also indicates the code-separated type. In addition, Zl (1=1.2
．． ...n) is the zone (z1=22=...=zn=z
), Dt (1=1 t 2 t”'n ) is a decimal number. The part zlnt (1=1 , 2 , ・n ) represents one digit of the numerical value with one byte. Also, SDi (l
= 1121-n) represents a code and one digit of a numerical value in one byte, and the S* part represents only a code in one byte.

A decimal number expressed in this type of format is calculated by a decimal calculation circuit, etc., and a sign is added according to the calculation result.
Stored in memory or registers. This code addition is performed by a code addition circuit. In a conventional code adding circuit, a code is added to a specific position of input data (data to be processed). Generally, the data length (number of digits) of a decimal number that is the object of an operation is undefined. Therefore, in order to add a code to a calculation result using a code addition circuit, a positioning circuit is required to align the byte representing the code of the calculation result to a position where the code can be added in the code addition circuit. In addition, in order to output the data (calculation results) added with a code by the code addition circuit to a memory, etc., a positioning circuit is required to correctly align the position of the data according to the specifications of the receiving circuit. is necessary. That is, a conventional data processing device equipped with a code addition circuit has the disadvantage that alignment circuits are required before and after the code addition circuit.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to add a code to any position of the data to be processed, thereby eliminating the need for a positioning circuit for adding the code.
The object of the present invention is to provide a base number code addition circuit.

[Summary of the invention]

In this invention, an input data line for guiding decimal data to be processed including variable-length data to be processed or its divided data, code position determining means for determining the position of a code part, and code generating means to generate code part data are provided. and a code addition means that adds (sets) the code part data generated by the code generation means to the corresponding position of the processed data determined by the code position determination means according to the code addition designation information. provided. In a data processing device that handles decimal format decimal numbers, the code position determining means determines the data to be processed based on type 1 information regarding the data length of the data to be processed and type 2 information regarding the memory start address of the data writing optical area. Determine the code part position in . Further, the code generation means generates code part data depending on whether the data to be processed is positive or negative. On the other hand, in a data processing device that handles at least a zoned decimal number, the code position determination means uses the first type and second type information, and also the third type information indicating whether the code part is a prefix or a postfix. The code part position is determined based on the species information. Further, the code generation means generates code part data according to the positive, negative, data format of the data to be processed, and further, if necessary, the data of the code addition position in the data to be processed.

[Embodiments of the invention]

FIG. 3 shows a circuit configuration of a decimal code adding circuit according to an embodiment of the present invention. The data length of the data to be processed handled by this embodiment circuit is 32 bits (4 bytes). In FIG. 3, 10 is, for example, a 4-byte wide input data line that leads to processing target data DI (including variable-length processing data or its divided data), and 20
is a selection circuit. The selection circuit 20 includes selectors 21 and 22.
From, it becomes. Selector 21 is terminal S.

The selector 22 has a terminal S. Selector 2
1.22 is four 1-byte data DI that constitutes data DI according to the S input (2 bits). - Select one of each of the upper 4 bits and each of the lower 4 bits of DI3. This selector 21 is in the output permission state when the E input is "LOW", and is in the output high impedance state when the E input is "HIGH".On the other hand, the selector 22 does not have an output control function, Output is always enabled.

A control signal ZONB (“HIGH” indicates the zone format) indicating whether the data format (of the data to be processed) is a pack format or a zone format is connected to the terminal E of the selector 21.
Also, 2-bit code addition position information SP is supplied to the terminals S of the selectors 21 and 22. Information S
P is supplied from the code addition position determining circuit 30, and determines which byte part of the data DI on the input data line 10 the code addition position (code section data setting byte position) is targeted to (i.e., DI, ~D 3).

Here, the code addition position determination logic of the code addition position determination circuit 30 will be explained. First, to facilitate understanding of this decision logic, we will describe data transfer of calculation results to main memory. In this example, the sign addition circuit is 10
It is provided at the output stage of a decimal arithmetic unit V (not shown). The data added with a code by the code addition circuit is transferred to a main memory control circuit (not shown) as a result of the operation.

The calculation results are then written into the main memory in an optimal combination of write modes provided in the main memory control circuit, depending on the length of the data and the data write memory start address. In this example, as the write mode, MF'w
(Memorial word write from full word boundary), M
Hw (memory bar 7 word write from half word boundary), MBW (memory byte write from byte boundary)
There are three types available: data is always transferred to the upper level and main memory.

Examples of the data location in the main memory and the transfer sequence in this case are shown in FIGS. 4(,) to (d). Note that one word consists of 4 bytes, and Figure 4 (,) indicates the byte position "0".
” (full word boundary) 1 to 5 byte write status and transfer sequence (indicated by the number inside the circle), 4th
Figure (b) shows 1 from byte position “1” (byte boundary)
to 5-byte write state and transfer sequence are shown. Also, Fig. 4(c) shows the write state and transfer sequence of 1 to 5 bytes from byte position ``2'' (halfword boundary), and Fig. 4(d) shows the transfer sequence from byte position ``3'' (halfword boundary). 1 to 5 byte write status and transfer sequence are shown. In this example, the data width of the path that supplies write data to the main memory control circuit is 4 bytes (32 bits).

Write modes other than MFW (4-byte write)
I1M/, MBW), the write data is
Data is transferred right-aligned along this path. In this embodiment, the processing data width of the code addition circuit matches the data width of the path. Then, the write data is supplied to the code addition circuit in a right-aligned form on the input data line 10 shown in FIG.

Here, the relationship between the data on the input data line 10 (processing target data DI) and the code addition position (code section data setting byte position) will be described. First, the code suffix (first
Figure 2(a).

(b)), the sign addition position is the lowest byte (input data line 10), regardless of the length of the data on input data line 10 (4 bytes, 2 bytes, 1 byte).
(The data part of Nonoito position "3" above). This is because, as described above, the write data is supplied in a right-justified form on the input data line 10. In contrast, the code prefix (Figure 2 (c), (
In the case of (see d)), the code addition position differs depending on the data length and the data writing memory start address.

First, the lower two bits of the memory start address are "oo",
That is, in the case of writing from byte position "0" (full word boundary), if the data length of the read data (data to be processed) is 1 byte, the code addition position is the 79 byte position "0" on the input data line 10. 3" (lowest byte position). Similarly, if the data length is 2 bytes,
The code addition position is the data portion at position "2" on the input data line 10. Also, if the data length is 3 bytes, 2 bytes are transferred first as shown in Figure 4 (,), so the code addition position is the same as when the data length is 2 bytes. 2". Also, if the data length is 4 bytes, the code addition position is byte position "
0” (most significant byte position). Also, the data length is 5
If it is more than a byte, 4 bytes are transferred first, so the code addition position becomes byte position "0", just like when the data length is 4 bytes. However, if the data length is 3 bytes or 5 bytes or more, it is necessary to prohibit the addition of codes to the second and subsequent transfer data.

Next, the lower two bits of the memory start address are ltQl
The case of writing from ff, that is, byte position "1" (byte boundary) will be explained. In this case, Figure 4 (
As shown in b), one byte is first transferred regardless of the data length of the write data. Therefore, the sign addition position is always byte position "3" on input data line 10.
This is the data part of However, if the data length is 2 bytes or more, it is necessary to prohibit adding codes to the second and subsequent transfer data.

Next, the lower two bits of the memory start address are '10'',
That is, the case of writing from byte position "2" (halfword boundary) will be explained. First, if the data length of the write data is 1 byte, the code addition position is the data portion at byte position "3" on the input data line 10. On the other hand, when the data length is 2 bytes or more, as shown in FIG. This is the data part of However, if the data length is 3 bytes or more, it is necessary to prohibit the addition of codes to the second and subsequent transfer data.

Finally, the lower two bits of the memory start address are 11'',
That is, the case of writing from byte position "3" (byte boundary) will be explained.

In this case, as shown in FIG. 4(d), one byte is first transferred regardless of the data length of the write data. Therefore, the sign addition position is always the data portion of byte position "3" on the input data line 10. However, if the data length is 2 bytes or more, it is necessary to prohibit adding codes to the second and subsequent transfer data.

As is clear from the above description, the input data line 10
The code addition position (code part data setting byte position) for the above data DI depends on whether the data format is code prefix or postfix, the length of the data to be processed, and the lower two bits of the data write memory start address. Determined by Regarding the length of the data, the code prefix and the lower two bits of the memory start address are OO", '10
It has meaning when #. When the lower two bits of the memory start address are '00#', if the data length is 4 bytes or more, the code addition position is a fixed position (byte position '0') regardless of the data length. Similarly, when the data length is 2 bytes or more, the code addition position is fixed at a fixed position (2) regardless of the data length.
). Therefore, regarding the data length, the lower two bits of data length information indicating the data length) LENG
TH2 and a signal FULWDI indicating whether the data length is 4 bytes or more can be used instead.

Therefore, in this embodiment, the code addition position determination circuit 30 is constructed based on the above principle.

In this example, the code addition position determination circuit 3o receives data length information LENGTH2 (2 bits) as shown in FIG.
, signal FULWD 1 (logic "1" indicates that the data length is 4 bytes or more), lower 2 bits ADR82 of the data write memory start address, and signal LEAD 1 (logic 111# indicates whether or not the code is prefixed). 6-bit information 3 consisting of (indicating that it is a code prefix)
01, it is configured to output 2-bit code addition position information sp indicating the code addition position (code section data setting byte position) for the data DI on the input data line 10. The code addition position determination logic of the code addition position determination circuit 30 is shown in Table 1 below.

Table 1: X = 1 rrelevant The code addition position determination circuit 30 is a ROM addressed by information 301.

Referring again to FIG. 3, 40 is a code generation circuit.

The code generation circuit 40 includes an output 221 from the selector 22.
and 4-bit control information 401 are supplied. The code generation circuit 40 includes a code generation ROM 41 as shown in FIG.
, 42.

The code generation ROMs 41 and 42 are addressed by the concatenation information (8 bits) of the output 221 and the information 401, and the upper 4 bits 40 of the code part data (1 byte)
2. Output the lower 4 bits 403. Information 401 is control signals (control bits) ZONE, 5IGN, 5P
It consists of RT and ABSO. Signal 5IGN indicates positive or negative sign ('HIGH' is negative, 'LOW' is positive). Also, signal 5PRT indicates mixed sign type in zone format data (see Figure 2(,), (c) M). “HI” indicates whether the
Signal AB80 indicates whether absolute value conversion is specified (“HIGH” indicates code-separated type; “LOW” indicates code mixed type).
” is specified, “LOW” is not specified) 0 In addition, the signal Z
The same applies to ONE as described above.

When explaining the code generation logic of the code generation ROMs 41 and 42, a zoned decimal code table is shown in Table 2 below to facilitate understanding.

Now, the code generation logic in this embodiment is generally as shown below.

a) ZONE=″”x, ow' (pack format)
In the case of 5IGN-HIG) f' (positive), and π proof = 1H
If IGH' (absolute value conversion is not specified), 403=≠D (1); otherwise, 403-4C (2). Note that the output 402 (output from ROM 4 J) may be anything. This is zO
In the case of NE="L, OW" (packed format), the output 211 from the selector 21 (instead of the output 402 of the ROM 41) is used as the upper 4 bits of the code part data, as will be described later.

b) ZONE = "uxaH' (zone format), and 5PRT = "I(IGH') (code separation m >
(7) If ABSO=“HIGH” (absolute value conversion specified), 402=+2, 403=+O (3) regardless of 5IGN.

On the other hand, ABSO='''LOW' (no absolute value specified)
then depends on 5IGN, if S IGN = ”
If 5IGN = "LOW" (positive), then 402 = 42.403 = +D (4), if 5IGN = "LOW" (positive), 402 = 4
P2.403=B...(5).

c) ZONg = “HIGH” (zone format)
, and when 5PRT = “LOW” (mixed code type), 5IGN = “f(IGH” (correct), and ABSO
=6HIGH" (no absolute value specified), 402.403 are the upper and lower decimal numbers with a negative sign whose absolute value is the output 221 from the selector 22...
・(6) Otherwise, 402=≠3.403=output 221 (7).

In FIG. 3, reference numeral 50 denotes a buffer dart to which the upper 4 bits 402 of the code part data output from the code generation circuit 40 are supplied. The Nogutsu Fagut 50 has a terminal E, and when the E input is 'HIGH', the output is enabled.
Similarly, when it is "LOW", the output becomes high impedance. A signal ZONF knee is supplied to the terminal E of the TFA dart 50.

60 is a code setting circuit. The code setting circuit 60 includes selectors 616 to 613 and a decoder (2to4 decoder)
It consists of 62. The data DI6 on the input data line 10 is input to the ``'1# side input section of the selectors 6Jo to 613.
=DI3 is supplied. On the other hand, selector 61. ~61
The output 2 from the selector 21 is input to the ``0# side input section of 3.
Wired OR output (4 bits) of the output 51 from the output 50 (4 bits) and the code generation circuit 4
The concatenated information (1 byte) of the output 403 (lower 4 bits of the code part data) from 0 is commonly supplied as the true code part data SD. The selectors 610 to 6C have a terminal S, and depending on the S input, input data on the "'1" side (DI
o=DIs) or ``0# side input data (8D).Selectors 61.o to 613
The respective selected outputs are concatenated and outputted to the outside as coded data DO for the processing target data DI. The decoder 62 is supplied with code addition position information 5P (2 bits) from the code addition position determination circuit 30. The decoder 62 has a terminal E and is enabled when the E input is LOW. When the decoder 62 is enabled, it decodes the information SP and outputs the signal DECO=DEC3F.
) 1 to 'L0w# ('o') 6 Also, when the E input is 'HIGH', the decoder 62 outputs the information sp.
All signals DEQ to DEC3 are set to ``HIGH'' (
“1”). The control signal 5 is connected to the terminal E of the decoder 62.
ATH is supplied. Signal 5ATH is used when code addition is prohibited in the code addition circuit shown in Fig. 3, for example, when data to be processed (written data) longer than 4 bytes is output in several parts, or when code addition is not performed and the code is simply output. It is used when you want to pass data.

Next, the operation of one embodiment of the present invention will be explained.

The code addition circuit in Figure 3 uses unsigned data (
This is to add (set) a code to the processing target data DI). What is signed data? In the case of tsuku format, DI(i" 1 + 2 t...
This data consists only of n). The S part is indeterminate and may be anything. On the other hand, in the case of the zone format, unsigned data is data in which the lower 4 bits of all digits (bytes) represent a numerical value. The upper 4 bits and the code byte (code part data) part in the code separated format may be anything.

Now, it is assumed that such unsigned data is supplied to the code addition circuit shown in FIG. 3 (through the input data line 10) as processing target data DI. It is also assumed that this data is pack format data. First, the code addition position determination circuit 30 selects LEAD! , ADR8
Code addition position information sp (see Table 1) corresponding to 6-bit information 301 consisting of 2, LENGTH 2°FULWD 1 is output. When the code is placed after the code (LEAD1=“0”) as in the pack type in this example, the code addition position determination circuit 30 selects ADR82, LENGTH2, FULW.
Regardless of D 1, s p = “11” (i.e. “3”
) is output. This information SP is supplied to each terminal S of the selector 21 , 22 and the decoder 62 .

A “LOW” level signal ZONE indicating that the selector 21 is not in the zone format (that is, it is in the GUTSUKU format) is supplied to the terminal E of the selector 21. As a result, the selector 2 is in the output permission state, and the input Data D on data line 10
5p (=''1) of each upper 4 bits of Io%DIs
The data indicated by 1'), that is, the upper 4 bits of DI3, is selectively outputted as output 211. On the other hand, the selector 22 selectively outputs the lower 4 bits of the data DI3 as an output 221.

Output 221 (lower 4 bits of DI3) from selector 22 is supplied to code generation circuit 40.

The code generation circuit 40 includes ABSO, ZONE, 5IGN,
4-bit control information 401 consisting of 5 PRTs is also supplied.

When ZONg=''LOW'' (pack format), the code generation circuit 40 performs the following as shown in (1) and (2) of a).
Either D or +C corresponding to the signals 5IGN and ABSO is output as an output 403 (lower 4 bits of the output of the code generation circuit 40). At this time, the output 402 outputted as the upper 4 bits of the output of the code generation circuit 40 is unnecessary as described below, and therefore may be of any value.

That is, the output 402 from the code generation circuit 40 is supplied to the node buffer 50, but when the signal ZONB is at the LOW level, the output impedance of the buffer point 50 becomes low. , the wired OR output of the output 211 (upper 4 bits of DIs) from the selector 21 and the output 51 from the buffer gate 50 matches the output 211.

This is output 21 from output 211 and output 51.
This is the same as selecting option 1.

The output 211 (which is a wired-OR output of the output 211 and the output 51) and the output 403 from the code generation circuit 40 (the code generation ROM 4, ?) are connected, and the code part data 5D(1) and the like are connected. selector 61 as
0~6130°゛0'' input parts are commonly supplied.Data DI is supplied to the ``1# side input parts of selectors 610~613.
o#D1. is supplied. On the other hand, the decoder 62 decodes the information SP of SP="11" from the code addition position determination circuit 30, and sets only the signal DEC3 to the "LOW" level.

The selectors 610 to 613 select and output data DI and %DI, which are 1" inputs, in response to the signal DECO-DEC2 at the 'HIG)4' level. On the other hand, the selector 613 selects and outputs the data DI, %DI, which is at the 'LOW' level. In response to the signal DEC3 of
0" input code part data SD is selected and output. As a result, the code addition data DO in which the code part data SD is set instead of DIs is output from the code addition circuit. To be more specific, , in the case of the packed format, the output 4 from the code generation circuit 40 is used instead of the lower 4 bits of DI3.
03 (pack format code) is set.

Next, the operation when the data DI is zone format data will be explained. In this case, “
HIGH" level signal ZONE is supplied to each terminal E of the selector 21 and the buffer dart 50. As a result, the υ selector 21 becomes an output high impedance state, while the buffer dart so becomes an output enabled state. As a result, Output 211 from selector 21 and buffer gate 50
The wired-or output with output 51 from
matches. Output 51 from buffer dart 50 and code generation circuit 40 (code generation ROM 42 within)
The outputs 403 from the no-no buffer r-) 50 are concatenated and commonly supplied to the "0# side input parts of the selectors 61° to 6c as code part data SD. This corresponds to the output 402 from the code generation ROM 41 (within the code generation ROM 41).In other words, in the case of code addition processing for zone format data, both the upper and lower 4 bits of the code part data SD are generated by the code generation circuit 40. .Code generation circuit 4
The output 402°403 from 0 is the above-mentioned bx3) ~ (
5), e), (6), or (7). The data DIo to DI3 are supplied to the "'1# side input parts of the selectors 61o to 613 as described above. The selectors 61. to 613 are supplied with the signals DEC and -DEC.
3, select either the "1# side input data or the MO" side input data.

These signals DEC0 to DEC are output from the decoder 62, and when the signal 5ATH is 'LOW', the byte position r indicated by the information sp from the code addition position determination circuit 30
Only the signal DECi corresponding to iJ becomes "HIGH" level. As a result, the code addition data Do, in which the code part data SD is set instead of DIi in the data DI, is output from the code addition circuit. More specifically, in the case of the zone format, the outputs 402 (higher 4 bits), 403 (
(lower 4 bits) are set, and data portions other than DIi are passed through as is.

Next, a decimal code adding circuit according to another embodiment of the present invention will be explained with reference to FIG. Note that the same parts as in FIG. 3 are given the same reference numerals. In FIG. 7, 70 is a selection circuit. The selection circuit 70 is the selector 21
．． 72. The selector 72 has a terminal S to which information sp from the code addition position determination circuit 30 is supplied, and a signal Z.
It has a terminal E to which an output signal (5th side) from an inverter 80 that inverts the level of ONg is supplied. The selector 72, like the selector 22 in FIG.
) selects one of the lower 4 bits of data DI (1-=-DI3).However, unlike selector 22, selector 72 has an output control function, and E input (ZONE) When is ``LOW'', that is, when zone format is specified, the output is enabled, and also ``HIG)I
”, that is, when specifying the pack format, the output is “LOW”
(all 4 bits). As a result, when processing packed format data, before the data DI on the input data line 10 is confirmed, the output 221 of the selector 22 (for convenience, the same reference numeral as the output of the selector 22 in FIG. 3 is given)
(to all pars 0"). When the output 221 of the selector 72 is determined, the code generation circuit 40 can generate the code part data. When processing packed format data (that is, ZONF = "LOW") ), the code generation circuit 40 can generate and output the code part data (consisting of outputs 402 and 403) regardless of the output 221 as long as the above output 221'' is determined. Therefore, according to this embodiment, like the code addition circuit shown in FIG. 3, the data DI becomes reliable and D1. -DI.

Since it is not necessary to wait for one of the data to pass through the selector 22 and reach the code generation circuit 4θ before starting code part generation, it is possible to speed up the process of adding codes to packed format data.

Note that the processing operation of zone format data is similar to that of the code addition circuit shown in FIG.

By the way, in the code addition circuits of FIGS. 3 and 7, L
EAD 1, ADR82, LENGTH2, FUL
A code addition position determination circuit 3° is provided which outputs code addition position information sp based on 6-bit information 301 consisting of WD 1, but instead of this core circuit 3o, a LEAD
1 and 3-bit information BN indicating the number of transfer bytes to be transferred next (however, BN is "ooi".

It is also possible to use a code addition position determination circuit that outputs information sp based on 4-pit information consisting of either "010" or "100". The code addition position determining logic of this code addition position determining circuit is shown in Table 3 below.

Table 3 The above Table 3 shows that when LEAD 1 = "0#", that is, the sign is deferred, SP is 11 # (
r3J). In addition, Table 3 above shows that LE
When AD 1 = "1", that is, a code prefix, if the number of transferred bytes is 1 byte, 2 bytes, or 4 bytes, sp is IL' (r3J), '1'O' (r2J), ', respectively.
oo'(rOJ). This decision logic is
Transfer data (write data) is input data line 1
It is based on the fact that it is supplied to the sign determination circuit in a right-justified form at 0. Generally, the main memory control circuit is provided with a data transfer control circuit that manages the next number of bytes to be transferred (number of transferred bytes) BN. Therefore, when determining the code position, it is possible to use the number of transfer bytes BN generated by this data transfer control circuit. The circuit configuration of this data transfer control circuit is shown in FIG.

In FIG. 8, 91 is a register that holds the number of bytes remaining to be transferred. The register 91 is initially set with the data length of the data to be processed (actually, the number of bytes is i bytes less than the data length of the data to be processed). A register 92 holds the lower two bits of the memory start address of untransferred data. In the register 92, the lower two bits of the memory start address of the data to be processed are initially set.

The contents held in the registers 91 and 92 are supplied to a transfer byte number determining circuit 93. The decision circuit 93 has registers 91 and 92.
The number of transfer bytes BN is determined based on each content of . This BN is input to B inputs of the subtracter 94 and A of the adder 95.
input section. The A inputs of the subtracter 94 are supplied with the output from the register 91, and the B inputs of the adder 95 are supplied with the output from the register 92. The subtracter 94 subtracts B input data from A input data to calculate the next number of remaining transfer bytes. The subtraction result of subtractor 940 is loaded into register 91. As described above, the register 9 is initially set to the number of bytes that is less than the data length of the data to be processed. Therefore, when the next data transfer is the last data transfer regarding the data to be processed, the output from the subtracter 94 will not be negative, and the carry signal CRT from the subtracter 94 will be "false." The signal CRT is used to generate the signal 5ATI (when the code postfix is specified. That is,
If the sign suffix is specified, the signal CRY is "true"
(true), the signal 5ATH is “HIGH”
level, and code setting for the corresponding transfer data is prohibited. In contrast, the signal CRT is “false” (f
(alse), the signal 8ATH is set to the "LOW" level, and the code setting for the corresponding transfer data is permitted.In addition, if the code prefix is specified, the first data transfer regarding the processed data Only when this happens, the signal 5ATH is set to the "LOW" level. on the other hand,
Adder 95 adds B input data to A input data,
Calculate the lower two bits of the memory start address of the next transfer data. The addition result of adder 95 is loaded into register 92.

In the above embodiment, the code addition circuit that can be applied to either the pack format or the zone format data has been described. However, if the target is only data in either the pack format or the zone format, the circuit configuration may be changed. It becomes possible to simplify. For example, in the case of only the pack format, the code generation ROM 41 and the buffer dart 50 are unnecessary. Also, instead of the code generation ROM 42, the signal 5
R generates a 4-bit code according to IGN and ABSO
OM (or logic circuit) can be used. Furthermore, it is possible to eliminate the need for the selectors 21 and 22 in the example of FIG. 3, and the selectors 21 and 72 in the example of FIG. In this case, data D1. The upper 4 bits of the code part data S
The upper 4 bits of D may be used. Further, a code addition position determining circuit 30, a selector 61 . .about.612 and decoder 62 can be made unnecessary. In this case, signal 5
Supply ATH to terminal S of selector 613,
The connection information between I and the selected output of selector 6c is data D.
It should be O. In addition, transfer data (write data)
is supplied to the sign determination circuit in the input data line 10 in a left-justified form, for example, even if it is in standard format, the sign addition position for the data DI on the input data line 10 is ADR8λLENGTH2. etc., the selectors 2o and 21, the code addition position determination circuit 30, the selector 61 . 612 and a circuit corresponding to the decoder 62 are required.

On the other hand, if only the zone format is used, the selector 21 is not necessary. Further, the buffer dart of 5° is also unnecessary. In this case, the concatenation information of the outputs 402 and 403 from the code generation circuit 4o may be used as the code part data SD. Furthermore, even in the zone format, if only the code-separated data format is used, the code addition position data (selector 22
Since it becomes unnecessary to use the data corresponding to the output 221 of , the selector 22 can be made unnecessary, and the code generation circuit 4θ can be simplified.

Further, the code addition position determination logic depends on the specifications of the main memory control circuit and the method of writing data to the main memory, and is not limited to the above embodiment.

〔Effect of the invention〕

As described in detail above, according to the present invention, a code can be added (code set) to any position of the data to be processed. As a result, it is possible to eliminate the need for an alignment circuit for adding codes.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the data structure of packed decimal numbers, FIG. 2 is a diagram showing the data structure of zoned decimal numbers, and FIG. 3 is a decimal code addition circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of the main memory, and FIG.
The figure shows input and output signals of the code addition position determination circuit shown in FIG. 3, FIG. 6 shows the internal configuration of the code generation circuit shown in FIG. 3, and FIG. 7 shows another embodiment of the present invention. FIG. 8 is a circuit diagram showing the configuration of a decimal code addition circuit according to the present invention, and FIG. 8 is a diagram showing the configuration of a data transfer control circuit having a data transfer byte number determining circuit. 10... Input data line, 21, 22.616~
61m+72... Selector, 3o... Code addition position determining circuit, 40... Code generation circuit, 41,421° code generation ROM, 60... Code setting circuit, 62...
decoder. Applicant's Representative Patent Attorney Takehiko Suzue Figure 5 Jul Figure 6 Figure 7 Figure DI Figure s8 RY

Claims (3)

[Claims] (1) In a data processing device that handles pars-format decimal numbers, there is an input data line that leads to decimal data to be processed including variable-length data to be processed or its divided data, and information regarding the data length of the data to be processed. code position determining means for determining the position of a code section in the data to be processed on the input data line based on type 1 information and type 2 information regarding the memory start address of the data writing optical area; , a code generation means for generating code part data in response to a negative value, and a code generation means for generating the code part data generated by the code generation means into the processing target data determined by the code position determination means in accordance with the code addition designation information. 1. A decimal code addition circuit comprising: code addition means for adding a code to a corresponding position. (2) In a data processing device that handles at least zoned decimal numbers, an input data line that leads to decimal data to be processed including variable-length data to be processed or its divided data, and information regarding the data length of the raccoon data to be processed. The processing target data on the input data line is based on type 1 information, type 2 information regarding the memory start address of the data writing optical area, and type 3 information indicating whether the code part is a prefix or a postfix. a code position determining means for determining the position of the code part in the data; a code generating means for generating code part data according to at least the positive, negative and data format of the processed data; and the code part data generated by the code generating means. A decimal code addition circuit comprising code addition means for adding the following to a corresponding position of the processing target data determined by the code position determination means in accordance with code addition designation information. (3) The code generation means generates code part data according to the positive, negative, data format of the data to be processed, and the data of the part position of the data to be processed determined by the code position determination means. A decimal code addition circuit according to item 2 of the scope of the patent application, characterized in that: