JPS60151899A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To know a relief address easily by constituting the device so that the specific pin status will change only for a defective address on the basis of the internal signal such as a redundancy selecting signal outputted when a defective address set beforehand is coincident with an inputted address in the specific mode. CONSTITUTION:A redundancy selecting signal phir is inputted to one input terminal of an AND gate circuit 16 as well as a redundant word driver 5s. On the other hand, when a special condition deciding circuit 15 connected to a control terminal 14 is impressed by a voltage at a high level, it outputs a detecting signal phic, which is inputted to the other input terminal of the AND gate circuit 16. As a result, when a defective address is accessed, an output of the AND gate circuit 16 becomes a high level, and a MOSFET18 is turned on. Consequently since a leak current runs in a control terminal 18, a relief address (defective address) can be signaled if this current is detected with external device.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit technology and technology that is effective when applied to semiconductor memory devices, such as semiconductor integrated circuit technology that has a spare memory column or memory row and a redundant circuit. This article relates to techniques that are effective for use in storage devices.

[Background Art] In semiconductor storage devices such as RAM (Random Access Memory), as the capacity of memory arrays increases, the yield decreases due to defective bits or word line defects such as word line disconnections or short circuits. It becomes a problem. Therefore, a redundant circuit is provided to relieve defective bits and word line defects by replacing columns or rows with defective bits or word line defects in the memory array with separately prepared spare memory columns or memory rows. It has been proposed to improve the yield rate.

As one method of such a redundant circuit configuration, the present inventors have
means for setting a memory line containing the defective pin 1- or the address of the memory line (hereinafter referred to as defective at-1-nos);
An address comparison circuit is provided to compare the set defective address and the input address, and when the two match,
We have developed a method to select a spare memory column or memory row in place of the regular memory column or memory row.

FIG. 1 shows its schematic configuration.

That is, 1 is the address signal A x input from the outside.
Atray buffer 2 which forms internal address signals axi and a71 based on iLS is a decoder which decodes address signals based on internal address signals axi and axi supplied from address buffer 1. Reference numeral 3 denotes an at1nos comparison circuit having a defective address setting means therein, which compares the input address and the defective address based on the internal address signals axi and axi supplied from the address buffer 1, so that both A signal φi that causes the redundant decoder 4 to operate vj when there is a complete match.
j is formed and supplied to the redundant decoder 4. Then,
The redundant decoder 2 outputs a redundant selection signal φr for selecting the redundant word driver 5s, and also outputs an inhibition signal 1 for inhibiting the operation of the normal decoder 2.

This redundancy selection signal φr drives the redundancy word driver 5S, which drives the word line of the spare memory row that replaced the memory row of the defective address, and selects the word line of the spare memory row.

On the other hand, if both addresses do not match, the redundant decoder 4 outputs an enable signal φe, and the word line driver 5 selected by the decoder 2 at that time
is driven to select a regular word line.

By the way, in memory failure analysis and the like, in order to check whether the redundant circuit operates normally, it would be convenient if it could be known which address has been repaired by the redundant circuit without a disassembly test.

However, in a semiconductor memory equipped with a redundant circuit as described above, there is a disadvantage that it is not possible to know which address is being repaired as a defective address by the redundant circuit just by operating the memory and observing its output. There is.

[Objective of the Invention] An object of the present invention is to make it possible to easily know the defective address that has been repaired by a redundant circuit by simply observing the state of a predetermined pin while scanning the address and moving the memory. The purpose of this is to facilitate failure analysis and the like.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, the present invention provides, for example, in a semiconductor memory device equipped with an address comparison type redundant circuit, in a certain predetermined mode, when a preset defective address and an input address match, a redundant signal is output to 4-. By configuring the state of a specific pin to change only when it is a bad address based on an internal signal such as a selection signal, you can easily scan the address and observe the state of a specific pin. This achieves the above purpose of being able to know the relief address.

The present invention will be described in detail below along with examples.

[Embodiment] FIG. 2 shows an embodiment in which the present invention is applied to a dynamic RAM.

In the figure, 1. a and lb are address signals A
A row address buffer and a column address buffer receive internal complementary address signals axi, axl and ay i, ay i, respectively. Also, 2a,
2b receives the internal complementary address signals axi, axi and aY l + a V supplied from the row address buffer 1a and the column address buffer lb,
These are a row address decoder and a color 15 address decoder for forming a word line selection signal and a data line selection signal, respectively.

The word line selection signal generated by the row address decoder 2a is supplied to the word line driver 5, which selects and enables the word line driver corresponding to the address Axi.

Further, a data line selection signal formed by the -1- distribution RAM address decoder 2b is supplied to a column switch 7 provided for each data line in the memory array 6.

The memory array 6 consists of a storage capacitor and an address selection MO8FET (insulated gate type 1 to type'?B, v\effective ri).
The well-known 1MO8 type memory cells made up of transistors) are arranged in a 71-lix shape. A sense amplifier and the column switch 7 are provided for each data line in the memory array 6, and the column switch 7 corresponding to the address Ayi is connected via the column switch 7 turned on by the selection signal output from the column address decoder 2b. The data on one data line is amplified by the sense amplifier and supplied to the main amplifier 9. Data read from the memory array 6 is amplified by the main amplifier 9 and output to the input/output terminal 11 by the output buffer 10.

Furthermore, during writing, data supplied to the input/output terminal 11 is taken into the input buffer 12 and written into the memory cell in the memory array 6 selected by the address decoders 2a, 2b.

On the other hand, a spare memory row 6s is provided on one side of the -[- memory array 6. Although one spare memory row 6S may be provided, in this embodiment, a plurality of spare memory rows 6S are provided.

3 has internal defective address storage means capable of storing the address of a defective word line having defects such as defective bits or disconnections, and compares an address signal input from the outside with the defective address stored internally; This is an address comparison circuit that detects whether an input address matches a defective address.

This address comparator circuit 3 has a programming element such as a fuse, and by cutting the programming element or changing the resistance value, a defective address can be set. It has a built-in device with the same structure and configuration as the means.

Then, the input address is compared bit by bit with the defective address, and when all the pins 1 to 1 match those of the set defective address, a signal φXjJ is generated to operate the redundant decoder 4, In addition to being supplied to redundant decoder 4, decoder inhibit signal φe is formed and supplied to row address decoder 2a. Suddenly,
The redundancy decoder 4 is operated by the redundancy selection signal φr to form a high-level redundancy selection signal φr that selects a spare memory row, and is supplied to the redundancy word driver 5s. As a result, the redundant word 1-time 5s is driven, and the word line of the spare memory row 6s is brought to the selection level.

Furthermore, all operations of the row address decoder 2ai are inhibited by the decoder inhibit signal φe output from the redundant decoder 4, the word line driver 5 is set to a non-selected state, and the regular word line in the memory array G is set to the selected level. You will not be exposed to

On the other hand, if the input address does not match the defective address by 18, the redundancy decoder 4 does not output the high-level redundancy selection signal φr, but instead outputs the decoder enable signal φe. This enable signal φ
e is supplied to the row address decoder 2a, the decoder 2a is operated, the word line driver 5 corresponding to the input address Axi is driven, and the regular word line in the memory array 1 is brought to the selection level. .

Furthermore, in this embodiment, the chip select signal O8 and the row address strobe signal RAS supplied from the outside,
Signals φX, φy, φ that control internal circuits based on control signals such as color 11 address strobe signal CΔS
For example, the level of the signal applied to the internal signal generation circuit 13 forming the ma etc. and the control terminal 14 to which a control signal such as the chip select signal C8 is input is a high level (-1- 5V), a special condition determination circuit 15 is provided which detects this and outputs a predetermined internal signal φC.

This internal signal φC is input to the AND gate circuit 16 together with the redundancy selection signal φr output from the redundancy decoder 4. In addition, a switch MO is connected between the control terminal 14 other than the control terminal 14 to which the special condition determination circuit 15 is connected and the ground point of the circuit.
S ri' INTI 8 is connected and this MOS F
r' knee 1' + 8 is 1- ΔAND gate circuit 16
It is turned on and off by the output signal of L-).

Therefore, while applying a voltage higher than normal to the control 1 to roll terminals 14, such as the chip selenium 1 to terminals to which the C8 signal is applied, all word lines are connected while changing the address AX one after another. While scanning, control terminal 1 connected to MO8FET1.8
Monitor 7. Then, the redundant circuit (address comparison circuit 3
When the defective address repaired by the redundant decoder 4 is input and the spare memory row 6s is accessed, the redundant decoder 4 outputs a high-level redundant selection signal φr. In this embodiment, this redundancy selection signal φr is sent to the AND gate 1 in addition to the redundancy word driver 5s to the circuit 1.
One of the input terminals of 6 is input. On the other hand, the special condition determination circuit 15 connected to the control terminal 14 outputs a detection signal φC when a voltage of a higher level than normal is applied.
This is input to the other input terminal of the AND gate circuit 16.

Therefore, when a defective address is accessed, the outputs of AND gate 1 to circuit 16 are set to high level, and MO8F
ET18 is turned on. As a result, a leakage current flows through the control 1-roll terminal 18, so if this is detected by an external device, it can be used as a relief address (defective address).
can be known.

In the above embodiment, the output of the AND gate circuit 16 is changed to high level based on the redundancy selection signal φr outputted from the redundancy decoder 4 when accessing the relief address, thereby preventing leakage to a specific terminal (control terminal 17). However, instead of causing leakage to a specific terminal, the output of the 1l-AND gate circuit 1G is supplied to the output sofa 10, and when the outputs of the AND gate 1 to 16 become high level, The circuit is configured so that the output state of the output buffer 10 is set to high impedance. This makes it possible to distinguish between the low impedance state of the output terminal during normal operation and the high impedance state during defective At1NOS access, and to know the rescue address by monitoring the input/output terminal T-11. It may be possible to do so.

In addition, in the embodiment 1, a special condition determination circuit 15 for detecting a special condition such as a signal level higher than the normal signal level is provided at the appropriate controller 1 to roll terminal, and the circuit 15 detects a special condition such as a signal level higher than the normal signal level. However, instead of providing the special condition determination circuit 15 as described above, the special timing of control signals such as the C8 signal, RAS signal, CA, and S signal supplied from the outside can be determined. By providing a circuit for determining within the internal signal generating circuit 13 or separately, the signal 1 corresponding to the detection signal φC can be
No. 2- may be generated to cause leakage or the like to a specific pin.

Furthermore, if the memory has empty pins, these can be used as dedicated pins for setting the special conditions described in -.

Further, in the above embodiment, a spare memory row 6s is provided in parallel with the word line to replace a memory row containing a defective bit etc. with the spare memory row 6s, but a plurality of spare memory rows 6s are provided. A configuration is provided in which two or more defective addresses can be repaired, or a spare memory column and a sense amplifier are provided in parallel with the data line to replace a data line containing a defective bit etc. with a spare memory column. It can also be applied to

[Effect (1) In a dynamic memory equipped with a redundant circuit using the address comparison method, when a circuit for detecting special conditions or special timing of a control signal is connected to a specific pin and a certain predetermined mode is set.”1 1. In the redundancy selection number 44, which is output when the preset defective address and the input address match in the redundancy circuit, 1. (Next, since we configured the system so that the state of a specific pin changes only when it is a defective address, if we apply a signal or voltage from outside to set the predetermined mode as described above and scan the address, Due to the effect that the state of a specific pin changes automatically when the address is accessed, the state of the specific pin can be detected easily.
The relief address can be known immediately, which has the effect of making it easier to analyze memory defects and the like.

(2) In a dynamic memory equipped with a redundant circuit using the address comparison method, when a circuit that detects a special condition or a special timing of a control signal is connected to a specific pin, and a certain predetermined mode is set, the above-mentioned redundancy occurs. Based on the redundancy selection signal that is output when the defective address set in advance in the circuit matches the input address, the state of a specific pin changes only when the address is defective, so it can be used externally. By applying a signal or voltage to set a predetermined mode as described above and scanning an address, the state of a specific pin is automatically changed when accessing a relief address, so a simple circuit can be added. However, there is an advantage that it is possible to easily know that the memory has been repaired by the redundant circuit and its repair address without any influence on other circuits.

Hereinafter, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the present invention is not limited to the redundant circuit using the address comparison method as in the above-mentioned embodiments, but can also be applied to other types of redundant circuits.

[Field of Application] In the above explanation, the invention made by the present inventor will mainly be explained in terms of the field of application, which is the background of the invention, which is dynamic RAM.
Although the description has been made for the case where it is applied to static RAM, the internal memory array is composed of memory cells consisting of capacitors and MOSFETs, just like dynamic RAM. So-called pseudo-static RAM, which can be treated in the same way as static RAM due to the configuration of its peripheral circuits, or read-only RO
It can be used in all semiconductor memory devices equipped with redundant circuits such as read-only memory (M).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of an access system of a semiconductor memory device equipped with a redundant circuit, and FIG. 2 is a block diagram showing an embodiment in which the present invention is applied to a dynamic RAM. 1a... Row address buffer, 1b... Column address buffer, 2a... Row address decoder, 2b... Color 11 address decoder, 3°°.
・Address comparison circuit, 4...Redundant decoder, 5...
...Word line driver, 5s...Redundant word driver, 6...Memoria 1 noise, 6s...Spare memory row, 7...Column switch, 9...May 16
- amplifier, 10...output buffer, 11...input/output terminal, 12...input cover sofa, 13...internal signal forming circuit, 14...control terminal, 15
...Special condition judgment circuit, 16...AND gate circuit, 17...Specific pin (control terminal) 18
...Switch element (MOSFET), Ax i,
Ay i ...address signal, axi, amy,
ayi, ayi...internal complementary address signal, φr...
... Redundancy selection signal, φC... Internal signal (special condition detection signal).

Claims (1)

[Scope of Claims] 1. It has four rows or columns of spare memory, means for setting a defective address, and an address comparison circuit for comparing the set defective address with an input address;
A semiconductor memory device equipped with a redundant circuit that generates a signal to select a spare memory row or column when an input address matches a defective address, and which selects a spare memory row or column based on a predetermined signal supplied from the outside. 1. A semiconductor memory device comprising means for forming an internal signal, and the state of a specific pin is changed at the time of redundancy selection based on the internal signal and the redundancy selection signal. 2. A switch element is connected to the specific pin, and the switch element is turned on when redundancy is selected based on the -1=internal signal and the redundancy selection signal, so that leakage occurs at the specific pin. Claim 1
The semiconductor storage device described in 1.