JPS60144954A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce resistance at a node between wirings by laminating a conductor layer connected to one wiring while crossing the stepped section of the end of the other wiring on the node between the wirings of two kinds formed on a substrate without an insulating film. CONSTITUTION:A wiring 1 consisting of WSi and an oxide film 6 are formed on a semi-insulating GaAs substrate 10, and an Au wiring 2 is shaped. The oxide film 6 and the wiring 2 are coated with an oxide film 11, the oxide film 11 is bored just above a boundary 2'' between the wirings 1, 2, and an Au layer 3 is evaporated. A resist mask 13 is applied, and Au 3 is etched, thus completing the titled integrated circuit. According to the constitution, wiring material layers of two kinds can be connected by low resistance without increasing a special manufacturing process, and the method is useful for improving the degree of integration.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a technology for connecting first wiring material layers of a semiconductor integrated circuit.

In prior art semiconductor integrated circuits, direct connection of two types of wiring materials constituting the first wiring material layer facilitates the design of the integrated circuit and helps improve the degree of integration. The conventional process of connecting the first layer wiring materials is shown in Figure 1. In the figure,
As shown in FIG. A, a wiring 1 made of Schottky gate material (WS i ) is formed on a caAs semi-insulating substrate 10, and in FIG. Create a pattern like this. Next, as shown in Figure C, the insulating film 6 is removed by etching using the photoresist 9 as a mask to expose a part of the WS1 layer 1 and the GaAs semi-insulating substrate 10, and the second wiring material is deposited on the core as shown in the figure. Source/drain electrode material (AuGe/
(Au) is deposited to form wiring 2. Note that the second wiring material deposited on the photoresist 9 is lifted off together with the photoresist 9. When the connection part is laminated in the case where the conventional first layer wirings are directly connected to each other, the second wiring material layer 2' is placed on top of the first wiring material layer 1 due to the process.
The side wall at the connection part has a steep shape. In particular, the second wiring layer shown in FIG.
It becomes very thin at the boundary 2". Also, if the thickness of the wiring 1 is made larger than the thickness of the wiring 2, this boundary 2" becomes very thin.
There is a risk of it breaking at "(see 3' in Figure 6).

Therefore, the resistance at the boundary 2" becomes high and the current concentrates on the contact surface 4. Moreover, the contact surface 4 of the steep side wall
However, there is a problem in that it is difficult to form a good contact.

As a countermeasure to this problem, conventionally, these materials were connected by a second layer wiring. An example is shown in FIG.
In order to electrically connect the wirings 1 and 2, another wiring material 6 (second layer wiring) existing through the insulating film 6 is used to connect the wirings 1 and 2.
are connected through through holes 7 and 8, respectively.

This method requires the area of the through holes 7.8 that connect the wirings 1 and 2 and the wiring 6, and the area of the wiring B that connects these through holes 7.8, which increases the area of the IC chip. We were connected. As another measure,
It is possible to prevent current concentration by increasing the thickness of the wiring 2, but the thickness of the film is limited by the vapor deposition methods used in current IC manufacturing processes, and it is not possible to increase the thickness by electroplating. Even if the process is complicated, the unevenness of the IC chip surface becomes large, and
This may lead to an increase in the length of the l-th wiring or a disconnection.

Purpose of the Invention The present invention was made to solve these problems, and its purpose is to reduce the resistance at the connection point of the wirings 1 and 2 in the manufacturing process of two-layer wiring without adding any special manufacturing process. .

Structure and operation of the invention In the present invention, a contact is provided to the wiring 2 so as to straddle the step at the end of the wiring 1 on the connection point of the two types of wirings 1 and 2 that exist on the substrate without an insulating film interposed therebetween. Electrical connections are formed by laminating conductor layers (conductor layers for second J-th wiring).

FIG. 5 provides a detailed explanation of the present invention using an embodiment of the present invention. The figure shows a part of the manufacturing process of an IC using GaAs MESFET. Au material
A wiring 2 consisting of the following is formed. 6 is an oxide film. Diagram A
The steps up to the step shown in FIG. 1B are the same as those shown in FIG. 1, and FIG. 1B corresponds to the diagram in FIG.

Next, as shown in FIG.
Then, remove the interconnection film 11 directly above the pattern as shown in Figure E, evaporate the Au layer 6 which is an overlay wiring as shown in Fig. E, form a resist 16, and use this as a mask to etch the Au layer 3, as shown in Fig. F. obtain the structure of

Note that the through hole according to the present invention has a two-layer wiring structure f)
The IC process does not require any special manufacturing process. This is because the through holes are simultaneously created in the through hole forming process in the multilayer wiring process.

Effects of the Invention As described above, according to the present invention, a low-resistance connection between two types of wiring material layers in the first layer can be formed in the manufacturing process of two-layer wiring without adding any special manufacturing process, thereby simplifying the design of integrated circuits. This makes it easier and helps improve the degree of integration.

[Brief explanation of drawings]

Figures 1A-D are process diagrams of conventional interconnect connections, Figures 2 and 6 are diagrams showing conventional interconnect connections, respectively, and Figure 4 is another conventional interconnect connection process. Figures 5A to 5F are process diagrams of one embodiment of the present invention. Main code 1 = WSi layer (wiring 1), 2- Au or AuGe
Layer (wiring 2), 3... 26th self-wire (wiring 6), 4...
・Contact surface, 5... Upper contact surface, 10... GaAa semi-insulating substrate, 11... Oxide film Patent applicant Fujitsu Limited agent Patent attorney Gobe Tamamushi (one other person) Figure 1 Figure 2 Figure 3 Figure 2' Figure 4 Figure 5 Figure 5 Figure 3

Claims (1)

[Claims] A second wiring layer is provided at the end of the first wiring layer on the substrate, extending from the end surface to the top surface and in contact with the end, and a second wiring layer is provided on the second wiring layer by straddling the step at the end of the first wiring layer. A semiconductor integrated circuit characterized by stacking body layers to form electrical connections.