JPS60124873A - Protective circuit for input to mos type semiconductor device - Google Patents

Abstract

PURPOSE:To increase withstanding voltage by preventing the floating of a P well, making the potential of the P well the same as the lower potential of an N region connected to a source or an N region connected to a gate at all times and obviating positive potential to the N regions of the P well. CONSTITUTION:The potential of a P well 11 and an N region 10, a gate G, is made the same by a metallic electrode 17 because an MOSFET2 is conducted and the potential of N regions 10 and 13 is made the same on gate potential of VGS<O. An MOSFET1 is conducted and the potential of N regions 9 and 12 is made the same-that is, the potential of the P well 11 is made the same as that of a source S on gate potential of VGS>O. The MOSFETs 1 and 2 are not conducted when gate potential VGS is equal to O volt or is lower than the thresholds VT1, VT2 of the MOSFETs 1 and 2, but an MOSFET3 is conducted and the potential of N regions 19 and 9 is made the same. The potential of the P well 11 is made the same as that of the source S because the N region 19 is connected to the P well 11 by a metallic electrode 20.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a gate protection diode for an MO8 type semiconductor device for power use.

Conventional Structure and Problems Generally, when driving a power MO8FET, positive and negative potentials are applied to the gate. This is necessary in switching operation to speed up the voltage response, and in microwave operation to improve efficiency as in class 0. To meet those requirements, gate protection diodes must be bipolar. Although this purpose can be achieved by connecting two diodes in opposite directions, this results in the creation of an npn (or pnp) structure within the semiconductor substrate, which poses a problem in that the withstand pressure is limited.

FIG. 1 shows such a conventional example. In the figure, the resistant substrate 1-
An N-type epitaxial layer 1-2 is formed on the substrate 1 with a thickness of about 10 microns to constitute a substrate 1, and a gate 2 is formed on the surface of the substrate with a thickness of about 10 microns.
It is formed through a gate oxide film 3 with a thickness of 1 micron. P-type base region 4 and 1° self-aligned to gate 2
A source 6 is formed by ion implantation and diffusion, and the P base 4 and the N1 source 5 are short-circuited by the metal electrode 6.

Substrate 1 is the drain. A P-well 11 and N-type regions 9, 1o are formed on the surface of the substrate 1, and metal electrodes 7, 8 connect the source 6 of the main body MO8FET.
and is connected to gate 2 to form a gate protection circuit.

N-type regions 9 and 10, P-well 11, and substrate 1 form an npn transistor. The drain breakdown voltage is affected by the BV (collector-emitter breakdown voltage when the pace is released) of the npn transistor thus constructed. B
In order to increase vcEo, it is necessary to prevent the P-well 11, which acts as a base, from becoming a positive potential with respect to the N-type regions 9, 1o, which act as emitters. However, in the configuration shown in FIG. 1, since the P well 11 is floating, it is affected by the gate potential and drain potential that change to positive or angular directions, and this condition cannot be satisfied.

Similarly, there is a floating base n between the gate and source.
Since a pn transistor is incorporated, the breakdown voltage between the gate and source is also kept low. The parasitic transistors are shown in the figure by dotted lines.

OBJECTS OF THE INVENTION An object of the present invention is to improve the withstand voltage of a bipolar gate protection circuit to which both positive and negative voltages can be applied.

Structure of the Invention In the present invention, the P well 11 is not floating and is always at the same potential as the lower of either the N region 9 connected to the source S or the N region 10 connected to the gate G. The gate protection circuit is configured to prevent the P well 11 from becoming a positive potential with respect to the N regions 9 and 10.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention is shown in FIG. Numbers 1 to 11 correspond to those in FIG. However, the main body MO8FET in Figure 1
2 to 6 are omitted. The G and S arrows indicate connections to the gate and source of the body MO8FET, respectively.

N regions 9, 12, 10, 13.19 and insulating film 14a
, 14b, 14c) 1
5, 16.18, MO8FET1.2.

3 are made up. The metal electrode 17 has an N region of 12°1
3 and P well 11 are connected. Also metal electrode 2o
connects the N region 19 and the P well 11. Gate terminal G is connected to N region 10 and gate 16 of MO9FET1.
, the source terminal S is connected to the N region 9 and the gate 16 of MO8FET2. The drain, which is the substrate, is M
It is connected to the gate 18 of the O8FET 3 through a metal electrode 22.

When gate potential ■Gs<o, MO8FET2 becomes conductive and N regions 1o and 13 reach the same potential. Become.

t, game) It place VG3>O with a null, MO8FET
1 becomes conductive, N regions 9 and 12 have the same potential, that is, P well 11 has the same potential as source S.

Gate potential vGs-O volts or threshold value vT1. of MO8FETs 1 and 2. When lower than vT2, MO3F
ET1 and 2 are non-conductive, but the drain potential vDs
When becomes a high positive value, MO8FET3 becomes conductive and N regions 19 and 9 are at the same potential. N region 19 is metal electrode 2o
Yo! Since it is connected to the llP well 11, the P well 11 has the same potential as the source S. At this time, N area 9
Or 1o is emitter, P well 11 is base, substrate 1
The threshold value "T3" of MO8FET3 must be smaller than BvcEo of the parasitic transistor whose collector is "T3".

This is to fix the P well to the source potential before the drain potential vDs reaches the BvcEo of the parasitic transistor. Similarly, the threshold vT1 of MO8FETs 1 and 2
．． It is desirable that vT2 be lower than BVoEo of the lateral parasitic transistor between the N regions 9, 12, and 13°7peso 1c. In this way, the threshold vT1. vT2 and vT3 and Bvc of vertical and horizontal parasitic transistors
Once the relationship with EO is set, the gate-source breakdown voltage BV
Gs is the junction breakdown voltage between the N region 9 or 10 and the P well 11, and the source-drain breakdown voltage BVDss is the junction breakdown voltage between the P well 11 and the substrate 1.

Insulating films 14a and 1 directly below the gates 15 and 16.
4b and 14c are all the same, and may be the same as the gate insulating film of the main body MO8FET, but since the drain breakdown voltage is generally higher than the gate-source breakdown voltage, the gate 18
Since the highest voltage is applied to the insulating film 140, it is desirable that the insulating film 140 be thicker. Therefore, in the insulating film 14G,
A thick field oxide film (23 corresponds to this in Fig. 2) formed around the main body 1vfO3FET or a vapor phase growth insulating film (24 corresponds to this in Fig. 2) covering the gate of the main body MO3FET is formed. use

Since the channels directly under the insulating films 14a, 14b, and 14c may be of an enhancement type having a threshold value lower than the withstand voltage of the parasitic transistor, a special impurity introduction step for making them a depletion type is not necessary.

Note that, as is clear from the connection relationship described above, N areas 12 and 13 may be the same area, and area 19 may be the same area as area 12.
It may be a part of.

Above, we have described the case where the main body MO3FET is N-channel, but in the case of P-channel, the conductivity type can be reversed.Also, although we have described the protection circuit for N-channel MO8FET, the conductivity type can also be changed in the case of P-channel. Of course, it can be applied by changing it.

Effects of the Invention As described above, when applying positive and negative voltages to the gate, the P well 11 is always at the same potential as the N region on the lower potential side with respect to the N regions 9 and 10. Never forward biased. The breakdown voltage of the parasitic transistor between the gate and source or between the source and drain is not BVcEo but BVcEo (base 9 page-collector breakdown voltage). Generally B V CE○〈B
Since V CB○, in the present invention, the withstand voltage between the gate and source and between the source and drain is high.

A feature of the present invention is that it does not require any increase or change in the number of steps in order to solve the conventional problem of a reduction in breakdown voltage by introducing a protection circuit. All, main body MO8FE
Made in the T manufacturing process. This means that high voltage resistance can be achieved without increasing manufacturing costs.

As a result, even in the case of bipolar input, the high withstand voltage M
The O8FET can be manufactured easily, and both high speed and high voltage resistance can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a structural sectional view of a conventional gate protection circuit, and FIG. 2 is a structural sectional view of a gate protection circuit according to an embodiment of the present invention. 1...N-type semiconductor substrate, 9, 10, 12,
13°19...N region, 11...P well, 14a. 14b, 14c...gate insulating film, 15,
16゜18...Gate, 7, 8, 17, 20,
22...10 -2' Metal electrode.

Claims (2)

[Claims] (1) Main body MO8 formed on a first conductivity type semiconductor substrate
FET, a well region of a second conductivity type formed on one main surface of the FET, and a first well region of a first conductivity type formed in the well region. Second. the third and fourth regions, the first and second regions above;
A first. the first gate and the third region are connected to the gate of the main body MO8FET; the second gate and the first region are connected to the main body MO8FET;
To the source of 8FET, the third gate is connected to the main body MO8.
An input protection circuit for an MO8 type semiconductor device, characterized in that the input protection circuit is connected to the drain of a FET, and the second region and the fourth region are further connected to the well. (2) The insulating film directly under the first and second gates is
・It is formed of a gate insulating film of a MOSFET, the insulating film directly under the third gate is a thicker insulating film, and all channels directly under the gate are of an enhancement type. MO8 according to claim 1
Input protection circuit for semiconductor devices.