JPS6011396B2 - Semiconductor storage device drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor memory device that can completely eliminate the inconvenience that information written in a semiconductor memory device having non-volatile semiconductor memory cells disappears when power is turned on or military power is turned off. The present invention relates to a drive circuit.

With the spread of microcomputers, nonvolatile semiconductor memory is developing a wide range of application fields as peripheral memory.

Among them, MIOS, which allows data to be electrically rewritten.
Structure (Metal - 1ns mountain ator - Oxide - S
The range of applications of non-volatile semiconductor memory (e.g. electronics) is wider than that of other structures. This type of non-volatile semiconductor memory differs from normal semiconductor memory in that it retains the correct memory state during lightning source or interruption; It is necessary that the memory state is always correct throughout the time of insertion. By the way, as shown in FIG. 1, a conventional drive circuit for driving a semiconductor memory device includes a semiconductor memory device 1 and a logic circuit 2 that controls the semiconductor memory device 1.
, a first power supply terminal 3 to which a voltage for driving the logic circuit 2 is applied, inverters 4, 5, 6 and inverters 4 to 6 arranged between the semiconductor memory device 1 and the logic circuit 2.
The output terminals 8, 9, and 1 of the logic circuit 2 are connected to a second power supply terminal 7 to which a voltage for controlling the operation of the semiconductor memory device 1 is applied. The semiconductor memory device 1 is driven by supplying the signal to the terminals 11, 12, and 13 of the semiconductor memory device 1.

The operation of a logic circuit using a P-channel MOSFET will be explained below as an example. In the illustrated circuit, when the power is turned on, the voltage applied from the second power supply terminal 7 is applied to the first
If the voltage is applied from the power supply terminal 3 in time, the following inconvenience will occur.

That is, the logic circuit 2 is in a correct logic state when a voltage is applied from the first power supply terminal 3, and the output terminals 8 to 1 output a signal at the correct logic level, and the logic circuit 2 is in a correct logic state before the voltage is applied. Not in a logical state. Therefore, when the voltage is first applied from the second power supply terminal 7 as described above, the inverters 4 to 6 are in the operating state, and the first
Drive control is executed based on the signal level of the output terminal of the logic circuit 2 to which the state where voltage is applied from the power supply terminal 3 of the semiconductor memory device 1 has not yet been established, and the memory state of the semiconductor memory device 1 is inadvertently changed. let In a semiconductor memory device using a nonvolatile semiconductor memory as a cell, the above-mentioned change in memory state is not allowed.

Therefore, restrictions as shown in FIGS. 2a and 2b apply to the application and disconnection of voltage via the first power supply terminal 3 and the second power supply terminal 7.

FIGS. 2a and 2b are diagrams showing the time relationship between the first power supply terminal 3 and the second power supply terminal 7. After turning on the power, first, as shown in FIG. 2a, A voltage V, is supplied from the first power supply terminal 3, and then a voltage y2 is supplied from the second power supply terminal 7 after a time t, (t,>0) has elapsed as shown in FIG. 2b. do. voltage V, and V2
When the voltage is cut off, the voltage V2 is first applied as shown in Figure 2b.
It is then necessary to turn off the voltage V, as shown in FIG. 2a, after the expiration of time law 2 (t2>0). If the supply and disconnection of the voltages V, . However, in order to obtain a power supply circuit that satisfies the voltage application relationships shown in FIGS. 2a and 2b, it is necessary to take considerable measures to the power supply circuit itself, which increases the cost of the power supply circuit.

The present invention provides a drive for a semiconductor memory device that can eliminate the disadvantages of conventional drive circuits and further the disadvantage of rising circuit costs when using a power supply circuit that realizes a voltage application relationship to solve these problems. The circuit is provided with a priority circuit that can inhibit the application of voltage from the second power supply terminal until the voltage applied from the first power supply terminal reaches a value sufficient to drive the logic circuit, The feature of this circuit is that it always maintains the correct memory state through its operation.

The present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing an example of the configuration of a drive circuit for a semiconductor memory device according to the present invention, in which voltage application by the first power supply terminal 3 is substantially more effective than voltage application by the second power supply terminal 7. The priority circuit to be prioritized includes a voltage divider that divides the voltage of the first voltage supply terminal composed of resistors 14 and 15, and a second voltage supply terminal to which the voltage of the voltage divider is applied as an input and as a drive voltage. Inverter to which voltage of 7 is applied
16 and the output of the inverter 16 as one input,
A NAND to which the output of the logic circuit 2 is applied as the other input, the output terminal is connected to the semiconductor memory device 1, and a driving voltage is applied from the second voltage supply terminal 7.
It is composed of circuits 17, 18, and 19.

In the semiconductor memory device drive circuit of the present invention having the above configuration, the following circuit operations are performed.

For example, it is assumed that the voltage at the first power supply terminal 3 is divided in half by a voltage divider and input to the inverter 16. The output level of the inverter 16 is at a low level (logic "0") when the voltage at the second power supply terminal 7 is applied, while the voltage at the first power supply terminal 3 is not applied, and therefore , NAND circuit 1 7,1
The output levels of the input terminals 8 and 19, that is, the signal levels of the input terminals 11 to 13 of the semiconductor memory device 1 are fixed at logic "1", and the semiconductor memory device 1 is not affected in any way. On the other hand, even when the relationship of voltage application to the first and second voltage supply terminals 3 and 7 is opposite to the above, the signal levels of the input terminals 11 to 13 are fixed to logic "1". That is, in order to apply normal signals for driving the semiconductor memory device 1 to the input terminals 11 to 13, a predetermined voltage must be applied to both the first and second power supply terminals 3 and 7. . FIGS. 4a to 4f are diagrams showing voltage waveforms at each part shown in FIG. 3. As shown in FIG. 4a, a predetermined voltage V is applied to the first voltage supply terminal 3, In addition, except for the period from T to T2 when a predetermined voltage V2 is applied to the second voltage supply terminal 7 as shown in FIG. 4b, the input terminals 11 to 13 are as shown in FIG. 4f. It is fixed to logic "1" as follows. As is clear from FIG. 4d, the inverter 16
The level of the output point d of is always logic "1" at least during the period from T to L, and moreover, the output level of the logic circuit 2 becomes normal as shown in Fig. 4e during this period. A drive signal corresponding to the output level is applied to the semiconductor memory device 1. By the way, FIG. 4c shows the voltage change at the output point c of the voltage divider. In this way, the voltage division of the first power supply terminal 3 by the voltage divider causes the output of the inverter 16 to be set to logic "1" after the voltage applied to the logic circuit 2 reaches a value that allows the logic circuit to operate normally.
5 is a circuit diagram in which the priority circuit shown in FIG. 3 is realized by a MOS transistor circuit. In the figure, 20 and 21 are MOS transistor resistors that constitute a voltage divider; 22 is an inverter MOS transistor, 23 is a load MOS transistor, 24-26, 27-
29, 30 to 32 are MOS transistors forming a NAND circuit, and 33 to 35 are N transistors connected to the output terminals of the logic circuit 2.
One input terminal of the AND circuit and 36 to 38 are NAN
This is the output terminal of the D circuit.

Note that the MOS transistors 20, 21, 23, 26, 2
9 and 32 are depression type, and the others are enhancement type. As is clear from the above explanation, according to the drive circuit for a semiconductor memory device of the present invention, by adding a priority circuit, the voltage application from the second power supply terminal is
The voltage from the first and second power supply terminals can be substantially inhibited until it reaches a value sufficient to drive the logic circuit, and the timing of voltage application from the first and second power supply terminals can be controlled in the power supply circuit. Since there is no need to make the determination as shown in FIG. 2, all of the conventional inconveniences can be eliminated.

As shown in Figure 5, the priority circuit can be realized with a MOS transistor circuit, so all of the circuits shown in Figure 3 are integrated into a single semiconductor substrate as a MOS integrated circuit. be able to.

Furthermore, although the above explanation has been made by exemplifying the logic circuit operation using a P-channel MOS transistor,
OS transistor, complementary MOS transistor (CMOS
) or bipolar transistors can be used to implement the priority circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional example of a drive circuit for a semiconductor memory device.
FIGS. 2a and 2b are diagrams showing the power supply conditions required for the circuit, FIG. 3 is a diagram showing an embodiment of the driving circuit of the semiconductor memory device according to the present invention, and FIGS. The voltage waveform of each part of the drive circuit shown in FIG. 3 is a diagram showing 0, and FIG. 5 is a diagram showing a specific example of the configuration of the priority circuit. 1... Semiconductor storage device, 2? . . . Drive circuit for semiconductor storage device control, 3 . . . First power supply terminal, 4 to 6, 16 . . . Inverter, 7.
...Second power supply terminal, 8 to 10...
- Output terminals for semiconductor memory device control signals, 11 to 13...
... Semiconductor storage device drive signal input terminal, 14,1
5...Resistance for voltage division, 17-19...N
AND circuit, 20, 21...MOS transistor resistance, 23...Load MOS transistor 0 transistor, 2
2, 24...Drive MOS transistor, 24-26
, 27-29, 30-32...MO for NAND circuit formation
S transistor, 33-35...Input terminal, 3
6-38... Output terminal. Figure 1 Figure 2 Figure 5 Figure 3 Figure 4

Claims (1)

[Scope of Claims] 1. A semiconductor memory device, a logic circuit that controls the memory state of the semiconductor memory device, a first power source that drives the logic circuit, and a memory that controls the memory state of the semiconductor memory device according to the state of the logic circuit. A second power supply required to change the state and a priority for prohibiting the application of voltage from the second power supply to the semiconductor memory device until the first power supply voltage reaches a value sufficient to drive the logic circuit. The priority circuit includes a voltage divider that divides the voltage of the first power supply, and a voltage divided by the voltage divider as an input, and a second
an inverter to which a power supply voltage is supplied from the power supply, the output of the inverter as a first input, a memory state control signal from a logic circuit as a second input, and a power supply voltage to be supplied from the second power supply. 1. A driving circuit for a semiconductor memory device, comprising at least one 2-input NAND gate circuit, and an output of the 2-input NAND gate circuit is coupled to a semiconductor memory device. 2. The drive circuit for a semiconductor memory device according to claim 1, wherein all circuit elements are integrated within a single semiconductor substrate.