JPS5995681A - Pattern matching circuit - Google Patents

Abstract

PURPOSE:To perform precise matching regardless of the contrast of an image pickup object by composing a picture-element generating circuit from plural comparators which differ in reference comparison level stepwise, and generating a multilevel signal as an image pickup picture signal. CONSTITUTION:When the image pickup picture signal VS arrives, it is led to the respective comparators 11a-11d and compared with their reference comparison levels respectively to obtain its binary-coded signals. Their binary-coded outputs are outputted as four-bit parallel picture element signals, which are converted by a parallel-serial converting circuit 14 into a serial signal and stored in a picture memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in pattern matching circuits used in position recognition devices for zone electrodes and scribe lines, for example in the manufacturing process of semiconductor devices.

[Technical background of the invention and its problems]

Conventionally, as this type of circuit, for example, as shown in FIG.
A captured image signal VS obtained by an industrial television (ITV) camera or the like is binarized by a binarization circuit 1 and stored in the image memory 2 as a pixelated turn signal, and the pixelated pattern signal is There is a system that calculates the degree of coincidence between both /4' turn signals by performing a correlation operation on a reference pattern signal stored in advance in the reference memory 3 and a correlation circuit 4.

However, in such conventional circuits, the captured image signal is converted into pixels by the binarization circuit l, so when the contrast of the imaged object is clear and the level difference of the captured image signal is not obvious, Although it is possible to obtain inaccurate matching information to some extent, if the contrast of the imaged object is unclear, even a slight shift in the reference comparison level of the binarization circuit 1 will change the matching result, so the matching accuracy may be affected. The drawback was that it was impossible to improve.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern matching circuit that can perform accurate matching regardless of the contrast of an object to be imaged.

[Summary of the invention]

In order to achieve the above object, the present invention provides a pixelization circuit that
It consists of a plurality of comparators each having a stepwise different standard comparison level, and the captured image signals are input to each of these comparators to perform a level comparison, and each comparison output is output as a pixelated signal. This is what I did.

[Embodiments of the invention]

FIG. 2 is a circuit diagram of a pattern matching circuit according to an embodiment of the present invention. In this figure, the same parts as those in FIG. 1 are given the same reference numerals and detailed explanations will be omitted.

The difference in the configuration of the circuit of this embodiment from that shown in FIG. 1 is that the pixel conversion circuit is configured as a multi-value conversion circuit. That is, the pixelization circuit 10 includes four comparators zza
, zzb+zzc*27d, and these controllers and operators l1tt.

Reference voltage generation circuit 121 for 11b, 11a, 11d
Reference comparison levels having stepwise different values are supplied to L, 12b, 12c, and 12ti.

This reference comparison level is set to 1, for example, so that the maximum value of the captured image signal VS is divided into 5, and a voltage that exceeds the maximum value x 1 is applied. Then, the pixelization circuit 10 introduces the captured image signal VS into the comparison input terminals of the comparators 11&mlb, Ilc, and IId, performs level comparison with each of the reference comparison levels, and sends the comparison outputs to the buffers 13&r 13bT13c, 13ti.
It is output as a parallel pixelated signal via the . Note that 14 is a parallel-to-serial conversion circuit that converts the pixelized signal in parallel format into a serial format.

With such a configuration, when the captured image signal VS arrives, the captured image signal VS is transmitted to each comparator llh.
, llb, llC, 1lti, and are compared with the reference comparison levels ■, @, θ, ■, respectively, as shown in FIG. 3, and As, BS, C8, D
Each is binarized like S. These binarized outputs AS, BS, C8, and DS are output as 4-pit parallel pixelized signals, and are sent to the parallel-to-serial conversion circuit 1.
4, the signal is converted into a serial signal and then stored in the image memory 2.

In this way, with the circuit of this embodiment, the captured image signal V
As a result, S is converted into five values, so even if the contrast of the object to be imaged is unclear, it can be converted into pixels more precisely than in the case of binary conversion, and as a result, the accuracy is improved. Good matching can be performed.

Note that the present invention is not limited to the above embodiments,
For example, instead of converting into 5 values, it may be set to 3 values, 4 values, or more. In addition, the reference comparison level setting means, the structure of the comparator, etc. can be modified in various ways without departing from the gist of the present invention.

〔Effect of the invention〕

As detailed above, according to the present invention, the pixelization circuit is
It is composed of a plurality of comparators each having a standard comparison level that is different in stages, and the captured image signal is multi-valued using these comparators, so that highly accurate matching can be achieved regardless of the contrast level of the imaged object. It is possible to provide a pattern matching circuit that can perform pattern matching.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional J?turn matching circuit, and FIG. 2 is an embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of the turn matching circuit, and is a signal waveform diagram used to explain the operation of the circuit. i-priming circuit for lθ river, 11 a + 1 l b +
110+Z Z d...Comparator, 12a, 1
2b e12cr12d...Reference voltage generation circuit.

Claims (1)

[Claims] Pattern matching involves converting the captured image signal into pixels using a pixelization circuit, storing the pixelized signal in the image memory, and calculating the correlation between this pixelized signal and the reference/main turn signal read out from the reference memory to determine the degree of pattern matching between both signals. In the circuit, the pixelization circuit is composed of a plurality of comparators each having a stepwise different reference comparison level, and the captured image signal is inputted to each of these comparators to perform a level comparison, and each of the comparisons A pattern matching circuit characterized in that the output is output as a pixelized signal.