JPS5991723A - Latch circuit - Google Patents

Latch circuit

Info

Publication number
JPS5991723A
JPS5991723A JP57202390A JP20239082A JPS5991723A JP S5991723 A JPS5991723 A JP S5991723A JP 57202390 A JP57202390 A JP 57202390A JP 20239082 A JP20239082 A JP 20239082A JP S5991723 A JPS5991723 A JP S5991723A
Authority
JP
Japan
Prior art keywords
level
input
latch circuit
gate
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57202390A
Other languages
Japanese (ja)
Inventor
Hirokazu Fukui
宏和 福井
Hirohisa Karibe
雁部　洋久
Toshihiko Matsumura
俊彦 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57202390A priority Critical patent/JPS5991723A/en
Publication of JPS5991723A publication Critical patent/JPS5991723A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To inhibit outputs Qn+1, Qn+1' from both going to 1 or 0 level by connecting an NOR gate or an NAND gate to an inverter in wired logical connection. CONSTITUTION:The NOR gate NOR and the inverter INV3 are connected in wired logic mode.The truth table of the latch circuit formed in this way is as shown in Table 1, and when the input B is at level 1 the Qn+1 output is at 0 level at all times and the Qn+1' goes to level, and both the outputs do not go to level 1. In using an NAND gate NAND in place of the NOR gate, the truth table is shown as Table 2, and when the input B is at level 0, the Qn+1 output goes always to level 0 and the Qn+1' goes to level 1 at all times. Thus, both the outputs do not go to 1 level together. Thus the outputs Qn+1 and Qn+1' are inhibited from going both to level 1 or 0 at the same time.

Description

【発明の詳細な説明】 （ａ）　　発明の技術分野 本発明は、最少ゲート数で、かつ常に出力がＱｎ＋１＋
可活耳の関係になるように構成したラッチ回路に関する
。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention has a minimum number of gates and always outputs Qn+1+
This invention relates to a latch circuit configured to have a movable ear relationship.

（ｂ）　　従来技術と問題点 従来のラッチ回路を第１図を用いて説明する。(b) Conventional technology and problems A conventional latch circuit will be explained using FIG. 1.

第１図は、従来のランチ回路の一構成例を示す図である
。図において、ＩＮＶＩ並びにＩＮＶ２１−ｔインバー
タである。FIG. 1 is a diagram showing an example of the configuration of a conventional launch circuit. In the figure, they are INVI and INV21-t inverters.

一般にラッチ回路としては、第１１閑に示すようにイン
バータＩＮＶＩとインバータＩＮＶ２と全ワイヤード＃
Ｐ理接続したものが用いらｔている。かかる第１図に示
すランチ回路の真丹値表ｒｒｉ表１の如くηる。In general, a latch circuit consists of inverter INVI, inverter INV2, and all wired wires as shown in the 11th line.
P-connected ones are used. The true value table rri of the launch circuit shown in FIG. 1 is as shown in Table 1.

表　　１ すなわち、かかる従来のランチ回路では、′０“レベル
より、”　ｉ　”レベルが優位となるようにしている。Table 1 That is, in such a conventional launch circuit, the ``i'' level is more dominant than the ``0'' level.

したがって、かかる従来のラッチ回路では、以下の欠点
が生じるものであった。′Ｔなゎち、入力端子Ａ、Ｈに
、同時に″１″レベルがきた場合、表１からもわかるよ
うに、出方。。＋ｌ　。Therefore, such conventional latch circuits have the following drawbacks. If ``1'' level comes to input terminals A and H at the same time, as can be seen from Table 1, the output will be different. . +l.

Ｑｎ＋＋　　ＬｄともにＩＩ　Ｉ　ＩＩレベルとナリ、
Ｑ　ｎ　＋１　＋Ｑｎ−１１のＩｙＪ係が乱れる仁とに
なる。したがって、かかるランチ回路やフリップフロッ
プを縦続接続する場合、面接接続することができないと
いう欠点がｔ）った。Both Qn++ and Ld are at II I II level,
The IyJ section of Q n +1 +Qn-11 becomes a disturbed Jin. Therefore, when such launch circuits or flip-flops are connected in cascade, there is a drawback that they cannot be connected face-to-face.

（Ｃ１発明の目的 本発明は、７５≧かる従来のラッチ回路の欠点に鑑み、
吊手ゲート数で、かつ常に出方が。ｎ＋１゜Ｑｎ＋＋　
の関係になるように構成できるラッチ回路を提供するこ
とを目的とする。(C1 Purpose of the Invention The present invention has been made in view of the drawbacks of conventional latch circuits such as 75≧.
The number of hand gates and the way they always come out. n+1゜Qn++
An object of the present invention is to provide a latch circuit that can be configured to have the following relationship.

（ｄ）　　発明の構成 本発明は、かかる目的を達成するために、第１の入力端
子から人力する論理レベルＡと、第２の入力端子から人
力する論理レベルＢを人力し、Ｑｎ＋＋＝（Ａ＋Ｑｎ）
＋Ｂまたは、Ｑｎ＋＋　＝Ａ　、Ｑ１＋Ｂの論理ｆｒ４
着を行い、該論、ｆ！Ｉ！演算の結果より、Ｑｎ＋１並
びにＱｎ−１＋’を出力すること全特徴とするものであ
る。(d) Structure of the Invention In order to achieve the above object, the present invention manually inputs a logic level A from a first input terminal and a logic level B from a second input terminal, and calculates Qn++=(A+Qn )
+B or Qn++ =A, logic fr4 of Q1+B
I made a decision and discussed the topic, f! I! The entire feature is that Qn+1 and Qn-1+' are output from the result of the calculation.

（ｅ）　　発明の実施例 以下、本発明のう、子回路の一実施例を園に沿って詳細
に説明する。(e) Embodiment of the Invention An embodiment of the slave circuit of the present invention will be explained in detail below.

第２図は、本発明のう、子回路の一実施例構成図である
。図において、ＩＮＶ３はインバータ、Ｎｏ−Ｒはノア
ゲートである。FIG. 2 is a configuration diagram of an embodiment of a child circuit according to the present invention. In the figure, INV3 is an inverter, and No-R is a NOR gate.

第２図に示すラッチ回路では、Ｑｎ−１−−二（Ａ＋Ｑ
ｎ）十Ｂの論理演算を行えるように構成されている。In the latch circuit shown in Fig. 2, Qn-1--2 (A+Q
n) It is configured to be able to perform 10B logical operations.

シタがって、“０″レベルよりもパ１ルベルが有効とな
るようにワイヤード論ア１１措成をとっていることがわ
かる。よって、かかる第２図に示す表　　　２ すなわち、表２に示すＸ理（ｉｉ表からも明らかな如＜
、Ｂ入力が６１″レベルならば、いつもＱｎ＋１出力は
０”レベル＋Ｑｎ＋ｔ　出方は６１”レベルとなる。し
たがって、Ｑｎ＋１出力並びにＱｎ−ｒ−＋出力がとも
に″１″レベルになることはない０ 次に、本発明のラッチ回路の仙、の実施例を亀３図を用
いて説明−する。Looking back, it can be seen that the wired logic is constructed in such a way that the pulse is more effective than the "0" level. Therefore, Table 2 shown in FIG.
, if the B input is at the 61" level, the Qn+1 output will always be at the 0" level +Qn+t and the output will be at the 61" level. Therefore, both the Qn+1 output and the Qn-r-+ output will never be at the "1" level. Next, an embodiment of the latch circuit of the present invention will be explained using Figure 3.

第３図は、本発明のランチ回路の１１１シの実施例も′
ｑ構成図ある。図において、ＩＮＶ４　［インバータ。FIG. 3 also shows a 111th embodiment of the launch circuit of the present invention.
There is a configuration diagram. In the figure, INV4 [Inverter.

ＮＡＮＤはナントゲートである。NAND is a Nant gate.

第３図に示ｒジソチ１問路では、Ｑｎ＋にＡ−Ｑｎ十Ｂ
の論鯉淀り′Ｆを行えるようにオフ・７成ｒ炙れでいる
。したがって、”　１　”レベルよりも″０″レベルが
有効となるようにワイヤード論理（・Ｐ成をとっている
ことがわかる。上つ°Ｃ１かかる角Ｘ３図に示すラッチ
回路の真理１１Ｉ′１表は表３の如くなる。In the first question shown in Figure 3, A-Qn0B is added to Qn+.
The theory is that the carp should be roasted off to 7sei so that it can be used as a carp. Therefore, it can be seen that the wired logic (・P configuration) is adopted so that the "0" level is more effective than the "1" level. is as shown in Table 3.

表　　　３ すなわち、表３に示すν（理仙表からも明らかな如く、
Ｂ入力が″０″レベルならば、いつもＱ　ｒ＋　＋　１
出力１ｄ”Ｑ”レベル＋　Ｑ−＋１”＋　１出力は”１
”レベルと斤るっし、たがってＱ　ＩＴ　＋１並びにσ
ｉ−萌−ｒ　出力がともに１”レベルになることはない
。Table 3 In other words, ν shown in Table 3 (as is clear from the Risen table,
If the B input is at the "0" level, it is always Q r+ + 1
Output 1d “Q” level + Q-+1”+ 1 output is “1”
``It is equal to the level, so Q IT +1 and σ
The i-moe-r outputs never reach the 1" level.

（ｆ）　　発明の効果 以上、詳細に説明した如く、本発明のう、子回路によれ
ば、伺加回跨なしで、Ｑ　ｎ　−１−１並びにＱｎ−１
青出力がともに６１ルベルまたは”０″レベルとなるこ
とを禁止できるので、４．１・１成も小型化できるとい
う効果が侑ら九ろ、。(f) Effects of the Invention As explained in detail above, according to the slave circuit of the present invention, Q n -1-1 and Q n -1 can be obtained without crossing the circuit.
Since it is possible to prevent both blue outputs from reaching 61 level or "0" level, the effect of making 4.1 and 1 generation smaller is that it is possible to do so.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のラッチ回路の一１２゛１成例を示す図、
第２図は本発明のラッチ回路の一実施例構成図、第３図
は本発明のラッチ回路の他の実施例構成図である。 図中、ＩＮＶＩ乃至ＩＮＶ４１−ｔ　イｙ　バー　タ、
ＮＯＲはノアゲート、ＮＡＮＤ　Ｆｉす／ドゲートであ
る。FIG. 1 is a diagram showing an example of a conventional latch circuit,
FIG. 2 is a block diagram of one embodiment of the latch circuit of the present invention, and FIG. 3 is a block diagram of another embodiment of the latch circuit of the present invention. In the figure, INVI to INV41-t,
NOR is a Noah gate, a NAND Fis/de gate.

Claims (2)

【特許請求の範囲】[Claims] （１）ｆ’０１の入力端子から入力するＨａ　Ｗレベル
Ａと、第２の入力端子から入力する論理レベルＢを入力
し、Ｑ　ｎ＋ｔ　＝（Ａ＋Ｑｎ　）＋Ｈの論理演算を行
い、該論理演算の結果より、Ｑｎ−４−１並びにＱｎ＋
１を出力することを特徴とするラッチ回路。(1) Input the Ha W level A input from the input terminal of f'01 and the logic level B input from the second input terminal, perform the logical operation of Q n + t = (A + Q n ) + H, and perform the logical operation of From the results, Qn-4-1 and Qn+
A latch circuit characterized by outputting 1. （２）第１の入力端子から入力する論理レベルＡと、第
２の入力端子から入力する論理レベル１３ヲ入力し、Ｑ
　１１　＋　１　＝：　Ａ　、　Ｑπ了１＝の論理演菊
゛を行い、該論理演ηの結果より、Ｑｎ＋を並びに４７
菖−を出力することを特徴とするラッチ回路。(2) Input the logic level A input from the first input terminal and the logic level 13 input from the second input terminal, and
11 + 1 =: A, perform the logical operation of QπRY1=, and from the result of the logical operation η, arrange Qn+ as 47
A latch circuit characterized by outputting an irises.
JP57202390A 1982-11-18 1982-11-18 Latch circuit Pending JPS5991723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57202390A JPS5991723A (en) 1982-11-18 1982-11-18 Latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57202390A JPS5991723A (en) 1982-11-18 1982-11-18 Latch circuit

Publications (1)

Publication Number Publication Date
JPS5991723A true JPS5991723A (en) 1984-05-26

Family

ID=16456695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57202390A Pending JPS5991723A (en) 1982-11-18 1982-11-18 Latch circuit

Country Status (1)

Country Link
JP (1) JPS5991723A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051610A (en) * 1989-02-21 1991-09-24 Mitsubishi Denki Kabushiki Kaisha SR latch circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051610A (en) * 1989-02-21 1991-09-24 Mitsubishi Denki Kabushiki Kaisha SR latch circuit

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