JPS5989433A - Bipolar type integrated circuit - Google Patents
Bipolar type integrated circuitInfo
- Publication number
- JPS5989433A JPS5989433A JP20071182A JP20071182A JPS5989433A JP S5989433 A JPS5989433 A JP S5989433A JP 20071182 A JP20071182 A JP 20071182A JP 20071182 A JP20071182 A JP 20071182A JP S5989433 A JPS5989433 A JP S5989433A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- epitaxial layer
- layer
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、バイポーラ型集積回W1<以F集槙回路’i
lcと略す)に関し、特にそのラッチアップの防止に特
徴を有する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides bipolar integrated circuit W1<F integrated circuit 'i
(abbreviated as lc), is particularly characterized by its prevention of latch-up.
現在、ICの入出力端子の電極パッド付近には、静電気
を原因とするサージや電源ラインからの誘導等によるサ
ージから内部回路の破壊を防止する為に、電極パッドと
内部回路間に抵抗体を接続してサージの侵入を阻止する
と同時に抵抗体と基板及びエピタキシャル層(以Fエピ
層と略す)間で作られるダイオード、に依って、サージ
パルスを吸収する方法が採用されている。Currently, resistors are placed between the electrode pads and the internal circuits near the electrode pads of the input/output terminals of ICs in order to prevent damage to the internal circuits from surges caused by static electricity or surges induced from power lines. A method has been adopted in which a diode is connected to prevent surges from entering, and at the same time absorbs surge pulses by using a diode formed between a resistor, a substrate, and an epitaxial layer (hereinafter abbreviated as F epilayer).
然し乍ら祈る構成を採用しても、1c17i:サージが
1」加されると上記した抵抗体とダイオードとから収る
保護回路が破壊される場合が多く、またその保護回路が
破壊されない場合でも、ツ゛−ジがIC内に発生するP
NPN構造を持つ寄生サイリスクのトリガーとなってラ
ッチアップを起し、電源とアース間で破壊を起す問題が
あった。However, even if a reliable configuration is adopted, when a 1c17i surge is applied, the protection circuit consisting of the resistor and diode mentioned above is often destroyed, and even if the protection circuit is not destroyed, the surge -P where the damage occurs in the IC
There was a problem in that it triggered a parasitic silicon risk with an NPN structure, causing latch-up and causing damage between the power supply and ground.
C−MOS Icの場合、Pチャンネル輌MO5Tのソ
ース→Nq基板→Pクエル→Nfヤンネル型MO5Tの
ソースの経路に依るPNPN構造にIミけるラッチアッ
プが比較的良く知られているが、バイポーラICに於て
も同、謙な寄生サイリスクのランチアップは発生してい
る。In the case of C-MOS ICs, it is relatively well known that latch-up occurs in the PNPN structure due to the path of P-channel MO5T source → Nq substrate → P-quel → Nf channel MO5T source, but bipolar IC The launch of the humble parasitic rhinoceros risk has also occurred in Japan.
第1図(a)(b)はバイポーラICK於けるラッチア
ップの原因を示したもので、tl)は−尋電梨半導体基
板、例えばP型シリコン糸板、i21 (31はP型分
陣を層(4)に依って島状に分離されたNf!1!エビ
層、(5)け該N型1ビ層(2)内に形成されたP 領
域、(6)はこのN型エビ層(2)に設けたN 型のコ
ンタクト領域、(7)は異っ九N型エビ層(3)に形成
されたN P N型トランジスタである。Figures 1 (a) and (b) show the causes of latch-up in bipolar ICKs. Nf!1! shrimp layer separated into islands by layer (4), (5) P region formed within the N type 1 layer (2), and (6) this N type shrimp layer. The N-type contact region provided in (2) is different from the N-type contact region (7), which is an N P N-type transistor formed in the N-type shrimp layer (3).
所る構成に於て、P+領域(6)をエミッタとし、N型
エビ層(2)をベースとし、P型分離層(4)をコレク
タとするPNP型の寄生ラテラルトランジスタ(10)
が形成され、またN型16層(2)をコレクタとし、P
型分離層(4)をベースとし、トランジスタ(7)のコ
レクタを構成しているN型エビ層(3)をエミッタとす
るN P N型の寄生トランジスタ(1りが形成され、
これ等のトランジスタ(101(Iりが第1図(b)の
等価回路で示される接続状態となっている。尚、0匂は
電源(Vcc)と寄生トランジスタ(lO)のベースと
の間に位置するベース抵抗で、N型エビ層(2)がコン
タクト頼*te+の部分で電源(Vcc)に接続されて
いる場合、この抵抗04はコンタクト領域からP+型囚
域(5)と分離層(4)とに挟捷れたエピ:fjj12
1の611分までの抵抗分とlよる。またQ樽は寄生ト
ランジスタ(11)のベースとアース(GND)との間
に存在するP型基板+l)の抵抗分である。In a given configuration, a PNP-type parasitic lateral transistor (10) has a P+ region (6) as an emitter, an N-type shrimp layer (2) as a base, and a P-type isolation layer (4) as a collector.
is formed, and the N-type 16 layer (2) is used as the collector, and the P
An N-type parasitic transistor (1 is formed,
These transistors (101) are connected as shown in the equivalent circuit in Figure 1(b). If the N-type shrimp layer (2) is connected to the power supply (Vcc) at the contact region *te+, this resistor 04 is connected from the contact region to the P+-type captive region (5) and the separation layer ( 4) Episode sandwiched between: fjj12
It depends on the resistance up to 611 minutes of 1 and l. Further, the Q barrel is the resistance of the P-type substrate +l) present between the base of the parasitic transistor (11) and the ground (GND).
この第1図(b)で示す回路罠於て両トランジスタ11
(+)、(lりの1lir鵞の積が1以上あると、サー
ジによるP形基板(1)の電位変動や、Vcc−GND
間電圧電圧変(上昇)等により何れかのトランジスタ1
+o)(lりに電流が流れると、各々のコレクタ電流が
ベース電流を供給し合う事になり、破壊(至るまで電流
を流し続ける。これはPNPN構造のサイリスク動作と
考オる私ができる。In the circuit trap shown in FIG. 1(b), both transistors 11
(+), (If the product of 1lir = 1 or more is 1 or more, the potential fluctuation of the P-type board (1) due to surges and the Vcc-GND
Due to voltage change (increase), etc., either transistor 1
+o) (When the current flows, each collector current supplies the base current to each other, and the current continues to flow until it is destroyed.I can think of this as the silisk operation of the PNPN structure.
この寄生サイリスクをターンオンさせる要因は色々考え
られるが何れの場合もベース抵抗0利場に依る電圧降下
がトランジスタ1lo)(+’l)のVBEに等しくな
る点を限界としてこの限界を越えた場合にラッチアップ
が生じる。There are various factors that can be considered to turn on this parasitic silicon risk, but in any case, the voltage drop due to the base resistance 0 voltage becomes equal to the VBE of the transistor 1lo) (+'l) is the limit, and if this limit is exceeded, Latch-up occurs.
木発情1はこのようなラッチアップ現象を防止する事を
目的としたもので、第2図、第6図を参照17つつ詳述
する。Tree estrus 1 is intended to prevent such a latch-up phenomenon, and will be described in detail with reference to FIGS. 2 and 6.
本発明の特徴とするところは、N型1ピ層(2)内に、
P 型領域(5)とP型分離層(4)とに挟まれPNl
′型の寄生トランジスタ(l(2)9ペースを構成して
いるp11所にN型の1ビ層(2)と同導電型の高濃度
領域直結するところにある。しかもこの高濃If領斌0
4)は第6図の上面図から明らかな如く、P+型領域(
5)とP型分離層(4)とが接近している間隙に設けて
いる。The feature of the present invention is that in the N-type 1-pi layer (2),
PNl is sandwiched between the P type region (5) and the P type separation layer (4).
' type parasitic transistor (l(2) 9 P11 is located in a place directly connected to the N type 1V layer (2) and a high concentration region of the same conductivity type.Moreover, this high concentration If region 0
4) is a P+ type region (
5) and the P-type separation layer (4) are provided in a gap where they are close to each other.
このように高濃度領域(14)をP 型@域(5)とP
型分離層(4)との間に設けてP 型頭域(5)に直結
する事に依って寄生トランジスタ(10)のベース・エ
ミック聞が短絡された事となり、この奇生トランジスタ
(lO)がONfる事はなくなる。その結果寄生サイリ
スクはWt成されず、ラッチアップ現象が生じる事はな
い。In this way, the high concentration region (14) is connected to the P type@region (5) and the P
By providing it between the type separation layer (4) and directly connecting it to the P type head region (5), the base and emitter of the parasitic transistor (10) are short-circuited, and this parasitic transistor (lO) will no longer turn on. As a result, parasitic silicon risk is not generated, and no latch-up phenomenon occurs.
尚、上記した説明に於てはN 型の高濃度領域4141
とP″−領域(6)とを直結する構成について記述した
が、高濃度碩域圓とP 領域(6)とを直結せずとも、
品濃度領M、−を形成するだけでも結果的に寄生トラン
ジスタ(10)のベース濃度を高める拳となるので、こ
のトランジスタのllpgは低下し、低電流@域例於て
はラッチアップ現象の抑制に寄与する。In the above explanation, the N type high concentration region 4141
Although we have described a configuration in which the P″-area (6) is directly connected to the
Even just forming the product concentration region M, - results in increasing the base concentration of the parasitic transistor (10), which reduces the llpg of this transistor and suppresses the latch-up phenomenon in the low current @ region example. Contribute to
本発明は以上の説明からり」らかな如く%1ビタキシャ
ルAj、ji内に、紐層内に形成した一得電型唄坂とこ
のエピタキシャル層を島状に分離し又いる分離層との間
隙にエピタキシャル層と同導電型の高濃度領域を設けて
いるので、バイポーラIcに放て生じる寄生トランジス
タのhpxを低rせし吟る事となり、ラッチアップ現象
を抑制する察が出来る。また本発明に於てはエピタキシ
ャル層内に形j戊したー導電型頼域と高濃度領域とを直
結しているので、寄生トランジスタのベース・Lミッタ
間を短絡し几事となり、寄生トランジスタの機能を完全
に抑え、結果的に寄生サイリスクは構成されずラッチア
ップ現象が生じる事はない。From the above description, it is clear that the present invention has a gap between the single-voltage-type Uta-saka formed in the string layer and the separation layer that separates this epitaxial layer into islands in the %1 bitaxial layer Aj, ji. Since a high concentration region of the same conductivity type as the epitaxial layer is provided in the epitaxial layer, the hpx of the parasitic transistor generated in the bipolar Ic is reduced and suppressed, and it can be assumed that the latch-up phenomenon is suppressed. Furthermore, in the present invention, since the open-conductivity-type dependent region and the high concentration region are directly connected in the epitaxial layer, it is convenient to short-circuit the base and L-mitter of the parasitic transistor. The function is completely suppressed, and as a result, no parasitic risk is formed and no latch-up phenomenon occurs.
4. t<J +fOのill単な説用第1図(a)
(b)はバイポーラ型ICに於けるラッチアップ現象を
説明する為の要部断面図及び等価回本
縮図、第2図、第6図けPす1バイポーラ型ICのe部
の断面図及び上面図であって、12H3)はエビタギシ
ャル層、(4)は分離層、(5)はP @」或、+10
)(l l)は寄生トランジスタ、(12193)は抵
抗、θ蜀は高濃度領域、を夫々示している。4. Simple illustration of ill for t<J +fO Figure 1 (a)
(b) is a cross-sectional view of the main part and an equivalent circuit diagram for explaining the latch-up phenomenon in bipolar type IC, and Figures 2 and 6 are cross-sectional view and top view of part e of bipolar type IC. In the figure, 12H3) is the evitagital layer, (4) is the separation layer, and (5) is P@'' or +10
)(l l) represents a parasitic transistor, (12193) represents a resistor, and θS represents a high concentration region, respectively.
Claims (1)
辷逆4電型の1ビクキシャル層と、該エピタキシャル層
を島状に分離する為の一導電型の分離層と、上記エピタ
キシャル層内に形成されたバイポーラ回路素子と、から
成り、上記基板とエピタキシャル層とに逆バイギス伏志
に嘔圧を印加するバイポーラ型集積回路に於て、上記エ
ピタキシャル層内に該)→内に形成した一導電型領域と
このエピタキシャル層を島状に分離している分離層との
間隙にエピタキシャル層と同導電型の高濃IW領域をt
fけた事を特徴とするバイポーラ型集積回路。 2)上記1ピタキシャル層内に形成した一電型叫域と高
濃度領域とを直結して我る特I!F請求の範囲第1項記
載のバイポーラ型集積回路。[Claims] 1) - A conductive substrate, and
It consists of one biaxial layer of an inverted quadrielectrical type, a separation layer of one conductivity type for separating the epitaxial layer into islands, and a bipolar circuit element formed in the epitaxial layer, and the epitaxial layer is connected to the substrate. In a bipolar integrated circuit in which a negative pressure is applied to the epitaxial layer, a region of one conductivity type formed within the epitaxial layer and this epitaxial layer are separated into islands. A highly concentrated IW region of the same conductivity type as the epitaxial layer is placed in the gap between the epitaxial layer and the epitaxial layer.
A bipolar integrated circuit characterized by f-digits. 2) A special feature that directly connects the one-electrode type screaming region and the high concentration region formed in the first pitaxial layer! F. A bipolar integrated circuit according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20071182A JPS5989433A (en) | 1982-11-15 | 1982-11-15 | Bipolar type integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20071182A JPS5989433A (en) | 1982-11-15 | 1982-11-15 | Bipolar type integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5989433A true JPS5989433A (en) | 1984-05-23 |
Family
ID=16428946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20071182A Pending JPS5989433A (en) | 1982-11-15 | 1982-11-15 | Bipolar type integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5989433A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6149461A (en) * | 1984-08-17 | 1986-03-11 | Nec Corp | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS513745U (en) * | 1974-06-25 | 1976-01-12 | ||
JPS51123579A (en) * | 1975-04-22 | 1976-10-28 | Toshiba Corp | Semiconductor integrating circuit |
JPS5616547A (en) * | 1979-07-20 | 1981-02-17 | Dainippon Ink & Chem Inc | Flame-resistant polyester resin composition |
-
1982
- 1982-11-15 JP JP20071182A patent/JPS5989433A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS513745U (en) * | 1974-06-25 | 1976-01-12 | ||
JPS51123579A (en) * | 1975-04-22 | 1976-10-28 | Toshiba Corp | Semiconductor integrating circuit |
JPS5616547A (en) * | 1979-07-20 | 1981-02-17 | Dainippon Ink & Chem Inc | Flame-resistant polyester resin composition |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6149461A (en) * | 1984-08-17 | 1986-03-11 | Nec Corp | Semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5077591A (en) | Electrostatic discharge protection for semiconductor input devices | |
US5166089A (en) | Method of making electrostatic discharge protection for semiconductor input devices | |
EP0032046B1 (en) | Circuitry for protecting a semiconductor device against static electricity | |
TWI485834B (en) | Combination esd protection circuits and methods | |
US5502328A (en) | Bipolar ESD protection for integrated circuits | |
JPH069018B2 (en) | Semiconductor structure | |
JPS5943827B2 (en) | protection circuit | |
KR930005191A (en) | Electrostatic discharge protection for complementary metal oxide semiconductor (CMOS) integrated circuits | |
EP0166581A2 (en) | Cmos circuit overvoltage protection | |
US4851721A (en) | Semiconductor integrated circuit | |
US4543593A (en) | Semiconductor protective device | |
WO1997010615A1 (en) | Electrostatic discharge protection network and method | |
US6215135B1 (en) | Integrated circuit provided with ESD protection means | |
US4712152A (en) | Semiconductor integrated circuit device | |
US3562547A (en) | Protection diode for integrated circuit | |
JPH03501669A (en) | Integrated circuit with latch-up protection circuit | |
JPS5848960A (en) | Semiconductor device | |
US5532896A (en) | Distributed silicon controlled rectifiers for ESD protection | |
JPS5989433A (en) | Bipolar type integrated circuit | |
JPH04280670A (en) | Gate voltage clamp type semiconductor device | |
US3597640A (en) | Short circuit protection means for semiconductive circuit apparatus | |
JP3158534B2 (en) | Semiconductor integrated circuit | |
JPH0478162A (en) | Protecting device for integrated circuit | |
JPH05315552A (en) | Semiconductor protective device | |
JPS5969956A (en) | Semiconductor device |