JPS5982774A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5982774A JPS5982774A JP19319282A JP19319282A JPS5982774A JP S5982774 A JPS5982774 A JP S5982774A JP 19319282 A JP19319282 A JP 19319282A JP 19319282 A JP19319282 A JP 19319282A JP S5982774 A JPS5982774 A JP S5982774A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- metal thin
- metal
- insulating film
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 89
- 239000002184 metal Substances 0.000 claims abstract description 89
- 239000010409 thin film Substances 0.000 claims abstract description 51
- 239000010408 film Substances 0.000 claims abstract description 26
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置にかかりとくにショットキードリ
アダイオードの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of a Schottky diode.
従来、金属シリサイド属を用いてショットキーバリアダ
イオードを形成する際に金属シリサイド層と配線金属薄
膜層の間にバリアメタル層として金属薄膜層を設け、シ
ョットキードリアダイオードの特性変化、特に熱による
特性変化を防止しているが、その際バリアメタル層配線
金属層の順に被着し、両者を、同時にエツチングすると
配線金属層下すべてにバリアメタル層が残り、この場合
バリアメタル層と半導体基板の密着性が悪い場合には、
配線金属層下がれを起こす可能性や、バリアメタル層と
配線金属層間で、配線金属層バターニングのための処理
中に、配線金属層とバリアメタル層間の電池作用により
配線金属層あるいは、バリアメタル層が、腐蝕され配線
の細りや断線が、発生しゃすくな夛信頼度の低下２歩留
の低下の原因となった。Conventionally, when forming a Schottky barrier diode using a metal silicide, a metal thin film layer was provided as a barrier metal layer between the metal silicide layer and the wiring metal thin film layer, and changes in the characteristics of the Schottky diode, especially due to heat, were avoided. However, if the barrier metal layer and the wiring metal layer are deposited in this order and both are etched at the same time, the barrier metal layer will remain under the wiring metal layer, and in this case, the barrier metal layer and the semiconductor substrate will be in close contact with each other. In case of bad sex,
There is a possibility that the wiring metal layer may fall down, or the wiring metal layer or barrier metal layer may deteriorate due to the battery action between the wiring metal layer and the barrier metal layer during the process for patterning the wiring metal layer between the barrier metal layer and the wiring metal layer. However, due to corrosion, thinning and disconnection of the wiring easily occurred, which caused a decrease in reliability and a decrease in yield.
以上の理由から、配線金属層被着前にバリアメタル層が
金属シリサイド金少なくとも覆う様、必要な部分のみ残
し、不要な部分をエツチングした構造がとられている。For the reasons mentioned above, a structure is used in which only the necessary portions are left and unnecessary portions are etched so that the barrier metal layer covers at least the metal silicide gold before the wiring metal layer is deposited.
しかしながら、この方法にも、バリアメタル層と隣接す
る配線金属層とのずれによるショートを防止するためバ
リアメタル層と隣接する配線金属層間の充分なマージン
を確保する必要があった。However, even with this method, it is necessary to ensure a sufficient margin between the barrier metal layer and the adjacent wiring metal layer in order to prevent short circuits due to misalignment between the barrier metal layer and the adjacent wiring metal layer.
本発明の目的は、上記従来の欠点を解消する新規なるシ
ョットキーバリアダイオードの構造を提供することであ
る。An object of the present invention is to provide a new Schottky barrier diode structure that eliminates the above-mentioned conventional drawbacks.
即ち、本発明は、半導体基板の一生面上ヲ援う第１の絶
縁膜と、該第１の絶縁膜に選択的に前記半導体基板に達
する様に設けられた第１の開孔部と、該第１の開孔部の
半導体基板ｐ面に設けられた金属シリサイド層と、該金
属シリサイド層を少なくとも榛う第１の金属薄膜と、該
第１の金属薄膜を少なくとも覆う第２の絶縁膜と、該第
２の絶縁膜に選択的に前記第１の金属薄膜に達しかつ前
記第１の金属薄膜のパターンより小さい形状に設けられ
た第２の開孔部と、該第２の開孔部を覆う第２の金Ｍ薄
膜とを有することに特徴がある。That is, the present invention includes: a first insulating film that supports the entire surface of a semiconductor substrate; a first opening provided in the first insulating film so as to selectively reach the semiconductor substrate; A metal silicide layer provided on the p-plane of the semiconductor substrate in the first opening, a first metal thin film that at least exposes the metal silicide layer, and a second insulating film that at least covers the first metal thin film. a second aperture provided in the second insulating film selectively reaching the first metal thin film and having a smaller shape than the pattern of the first metal thin film; It is characterized in that it has a second gold M thin film covering the portion.
次に、本発明をよりよく理解するために、従来の実施例
と比較しながら、本発明の実施例について説明する。Next, in order to better understand the present invention, embodiments of the present invention will be described while comparing with conventional embodiments.
第１図に従来のブヨットキーバリアダイオードのショッ
トキーコンタクト部分の断面図を示す。FIG. 1 shows a sectional view of a Schottky contact portion of a conventional Vjotky barrier diode.
半導体基板１の一生面上を覆う、第１の絶縁膜２と、該
第１の絶縁膜に選択的に前記半導体基板に達する様に設
けられた第１の開孔部３と該第１の開孔部の半導体基板
表面に設けられた金属ンリサイド層４と、該金属ノリサ
イド層を少なくとも覆う第１の金属薄膜５と該第１の金
属薄膜上に形成された第２の金属薄膜６によ多構成され
ている。A first insulating film 2 that covers the entire surface of a semiconductor substrate 1; a first opening 3 provided in the first insulating film so as to selectively reach the semiconductor substrate; A metal oxide layer 4 provided on the surface of the semiconductor substrate in the opening, a first metal thin film 5 covering at least the metal oxide layer, and a second metal thin film 6 formed on the first metal thin film. It is made up of many things.
金属シリサイド層としては、代表例として、白金７リサ
イド層が用いられる。また、第１の金属薄膜は、第２の
金属薄膜と金属シリサイド層間の反応を抑える目的で設
けられるバリアメタル層で、代表例として、チタン・タ
ングステン合金属などの高融点金属が使用される。第２
の金属薄膜は、配線金属薄膜で、代表例としては、アル
ミニウム層が用いられる。As a typical example of the metal silicide layer, a platinum 7 silicide layer is used. Further, the first metal thin film is a barrier metal layer provided for the purpose of suppressing the reaction between the second metal thin film and the metal silicide layer, and a high melting point metal such as a titanium-tungsten alloy is typically used. Second
The metal thin film is a wiring metal thin film, and an aluminum layer is typically used.
この従来の構造では、第１の金属薄膜５と隣接する第２
の金属薄膜σの間にパターニングの際のずれを見込んで
充分なマージンをとる必要がち漫、また、第１の金属薄
膜５を第２の金属薄膜６が、完全に檀っていない場合に
は、第２の金属薄膜６及びＣのバターニングのための処
理中に、第２の金属薄膜と第１の金属薄膜の間に電池作
用により第１の金属薄膜あるいは、第２の金属薄膜が腐
蝕され、配線の細シや、断線が発生しゃすくな力、信頼
度の低下９歩留の低下の原因となった。In this conventional structure, the first thin metal film 5 and the second metal thin film 5 are adjacent to each other.
It is often necessary to provide a sufficient margin between the metal thin films σ in consideration of the deviation during patterning. During the process for buttering the second metal thin film 6 and C, the first metal thin film or the second metal thin film is corroded due to battery action between the second metal thin film and the first metal thin film. This caused thin lines in the wiring, increased strength to cause wire breakage, decreased reliability, and reduced yield.
次に本発明の実施例を第２図に示す。半導体基板１の一
生面上ヲ嫌う、第１の絶縁膜２と、該第１の絶縁膜に選
択的に前記半導体基板に達する様に設けられた第１の開
孔ｓ３と、該第１の開孔部の半導体基板表面に設けられ
た金属シリサイド層４と、該金属シリサイド層を少なく
とも覆う第１の金属薄膜５と該第１の金属薄膜を少なく
とも櫟う第２の絶縁膜７と該第２の絶縁膜に選択的に前
記第１の金属薄膜に達しかつ前記第１の金ｈ４薄膜のパ
ターンより、小さい形状に設けられた第２の開孔部８と
、該第２の開孔部を捗り第２の金属薄膜６とを有した構
造となっている。Next, an embodiment of the present invention is shown in FIG. A first insulating film 2 that is exposed to the entire surface of the semiconductor substrate 1, a first opening s3 provided in the first insulating film so as to selectively reach the semiconductor substrate, and A metal silicide layer 4 provided on the surface of the semiconductor substrate in the opening, a first metal thin film 5 that at least covers the metal silicide layer, a second insulating film 7 that at least covers the first metal thin film, and the first metal thin film 5 that at least covers the metal silicide layer. a second opening 8 selectively reaching the first metal thin film in the second insulating film and having a smaller shape than the pattern of the first gold H4 thin film; The structure has a second metal thin film 6 extending therefrom.
以上の構造分とることにより、第１の金属薄膜５と隣接
する第２の金属薄膜Ｃの間にマージンが不要となり、か
つ、第２の金属薄膜及び第２の絶縁膜で第１の金属薄膜
を覆うため、第２の金属薄。By taking the above structure, there is no need for a margin between the first metal thin film 5 and the adjacent second metal thin film C, and the second metal thin film and the second insulating film can be used to separate the first metal thin film A second thin metal layer to cover.
膜と第１の金属薄膜間で、電池作用による不都合は起こ
らない。No disadvantages due to battery action occur between the membrane and the first metal thin film.
また、第２図において第１の金属薄膜上に形成する第２
のＰ縁膜は、第１の金属薄膜からの生成膜でもよいし全
く別の絶縁膜でもよい。In addition, in FIG. 2, a second metal thin film formed on the first metal thin film is
The P edge film may be a film formed from the first metal thin film or may be a completely different insulating film.
第１図は、従来のショットキーバリアダイオードの断面
図であり、第２図は、本発明の一実施例を示す断面図で
ある。
図中において、ｌ・・・・・・半導体基板、２・・・・
・・第１の絶縁膜、３・・・・・・第１の開孔部、４・
・・・・・金属シリサイド層、５・・・・・・第１の金
属薄膜、６・・・・・・第２の金属薄膜、７・・・・・
・第２の絶縁膜、８・・・・・・第２の開孔部、Ｃ・・
・・・・隣接する第２の金属薄膜である。FIG. 1 is a sectional view of a conventional Schottky barrier diode, and FIG. 2 is a sectional view showing an embodiment of the present invention. In the figure, l...semiconductor substrate, 2...
...First insulating film, 3...First opening, 4.
...Metal silicide layer, 5...First metal thin film, 6...Second metal thin film, 7...
-Second insulating film, 8...Second opening, C...
. . . Adjacent second metal thin film.
Claims (1)
絶縁膜に選択的に前記半導体基板に達する様に設けられ
た第１の開孔部と、該第１の開孔部の半導体基板表面に
設けられた金槁シリサイド層と、該金属シリサイド層を
少なくとも穆う第１の金属薄膜と、該第１の金属薄膜を
少なくとも覆う第２の絶縁膜と、該第２の絶縁膜に選択
的に前記第１の金属薄膜に達しかつ前記第１の金属薄膜
のパターンより小さい形状に設けられた第２の開孔部と
、該第２の開孔部を覆う第２の金属薄膜とを有すること
を特徴とする半導体装置。a first insulating film extending over the entire surface of a semiconductor substrate; a first aperture provided in the first insulating film so as to selectively reach the semiconductor substrate; and the first aperture. a metal silicide layer provided on the surface of the semiconductor substrate in the area; a first metal thin film that at least covers the metal silicide layer; a second insulating film that at least covers the first metal thin film; a second opening selectively formed in the insulating film to reach the first metal thin film and having a smaller shape than the pattern of the first metal thin film; and a second opening that covers the second opening. A semiconductor device comprising a metal thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19319282A JPS5982774A (en) | 1982-11-02 | 1982-11-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19319282A JPS5982774A (en) | 1982-11-02 | 1982-11-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5982774A true JPS5982774A (en) | 1984-05-12 |
Family
ID=16303832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19319282A Pending JPS5982774A (en) | 1982-11-02 | 1982-11-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5982774A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319974A (en) * | 1988-06-20 | 1989-12-26 | Nec Corp | Semiconductor device |
| JP2014241436A (en) * | 2007-03-26 | 2014-12-25 | 住友電気工業株式会社 | Schottky barrier diode and process of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5441673A (en) * | 1977-09-09 | 1979-04-03 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPS5578578A (en) * | 1978-12-11 | 1980-06-13 | Toshiba Corp | Manufacture of schottky barrier diode |
-
1982
- 1982-11-02 JP JP19319282A patent/JPS5982774A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5441673A (en) * | 1977-09-09 | 1979-04-03 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPS5578578A (en) * | 1978-12-11 | 1980-06-13 | Toshiba Corp | Manufacture of schottky barrier diode |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01319974A (en) * | 1988-06-20 | 1989-12-26 | Nec Corp | Semiconductor device |
| JP2014241436A (en) * | 2007-03-26 | 2014-12-25 | 住友電気工業株式会社 | Schottky barrier diode and process of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5631499A (en) | Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics | |
| US4263606A (en) | Low stress semiconductor device lead connection | |
| JPH04155835A (en) | Manufacture of integrated circuit device | |
| US5128745A (en) | Semiconductor device with thin film resistor | |
| US4754318A (en) | Semiconductor device | |
| US6538301B1 (en) | Semiconductor device and method with improved flat surface | |
| US4916397A (en) | Semiconductor device with bonding pad | |
| US4394678A (en) | Elevated edge-protected bonding pedestals for semiconductor devices | |
| JPS5982774A (en) | Semiconductor device | |
| GB2205684A (en) | Lift-off method of fabricating electrodes for semiconductor devices | |
| US6995082B2 (en) | Bonding pad of a semiconductor device and formation method thereof | |
| JPH03159152A (en) | Manufacture of bump electrode | |
| KR100256271B1 (en) | Metal wiring method of semiconductor device | |
| JP2850380B2 (en) | Method for manufacturing semiconductor device | |
| JP3413653B2 (en) | Semiconductor device | |
| JP2803188B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JP3351878B2 (en) | Semiconductor device and method of manufacturing the same | |
| JPS5933252B2 (en) | Manufacturing method of semiconductor device | |
| KR100197129B1 (en) | Forming method for metal wiring in semiconductor device | |
| JPH0282623A (en) | Semiconductor integrated circuit device | |
| JPS62281356A (en) | Manufacture of semiconductor device | |
| JPS61141157A (en) | Manufacture of semiconductor element | |
| JPH03132036A (en) | Manufacture of semiconductor device | |
| JPH0126533B2 (en) | ||
| JPS6133257B2 (en) |