JPS5975780A - Method and device for correcting video signal for inhibitingvideo signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Although the present invention prohibits the recording of video signals in video tape recorders (V'l'R), it still , 1 to allow reproduction of the video signal in
This article relates to a technique for changing bidet No. 16.

In the prior art, it has been proposed to modify the video signal to inhibit the recording of video signals by modifying the vertical blanking interval at a certain point. Thus, U.S. Patent Y-3,
In No. 963,865, all but 1.5 pulses of the vertical synchronization pulses within the vertical interference interval are removed, and the remaining 1 and 5 synchronization pulses are determined by the appropriateness of the television receiver. However, it is insufficient for proper operation of conventional V'l' Ji. In U.S. Patent No. 4.100゜575,
This vertical blanking interval is adapted to be modified by replacing several vertical synchronization pulses 2 and subsequent equalization pulses with simulated equalization pulses.

However, in these 4m to 1m distances, the 4m to 1m interval is replaced by a locally generated vertical spacing, which causes the unreasonable It is relatively easy to record and/or make the P+%K function available.

Therefore, 5. Ichimoku H-Jll-J of the present invention: amends the video signal No. 16 to prevent the recording of video signals that are not relatively easy to violate or destroy, and that represent small commercial record keeping. Su, 5
To provide a method and apparatus for.

One of the features of the present invention is a modified video (,li-
In order to prevent the recording of the video signal while recording the video signal in response to the video signal, it is rare to modify the video signal in order to inhibit the recording of the video signal while designing the television receiver. A method is provided that describes the process of converting a video signal into an LE with a stagnant signal.

Since conventional VTRs limit their operation to a fixed field length of the video signal that must be exceeded, a modified video signal with a variable field length can be recorded in this way. Can't be licked. However, the unusual field length of this modified video signal does not significantly affect normal television reception and viewing. Thus, the modified bidet No. 100 can be broadcast with little or no problems in recording and filming.

Preferably the field length of bidet No. 1g is
,'1. 'The line is modified by adding or removing the line by repeating the line at the end of each field of the video signal. To prevent image sottering in conventional television reception of broadcast-modified video signals, the field length of the first video signal is varied by a ratio no greater than, on average, three fields per line of video signals. It is preferable to have 7 days.

In order to 6yiC the modified bidet No. 1d Niu, 1
It is desirable to change the field length of the video signal such that the long-term average value of the field length of the corrected video signal is equal to the field length of the uncorrected video signal.

In an embodiment of the present invention, which will be described in detail below, the process of changing the field length of the video signal is performed by sequentially adjusting the length of the video signal to be corrected. Video (consisting of recording line g and reading this line from memory, said line being approximately sequentially read out), one for each short and extended field in the corrected video signal. Lines are removed from the length of the individual fields and read out again to generate the .

This invention V also. Includes an apparatus for converting between a video signal consisting of a field of constant length of lines of a video signal and a modified video signal consisting of a field of variable length of a line of video signal No. 16 and the apparatus includes: a memory device; a device for storing one video signal line of the video signal in the memory device; a device for extracting a video signal line from the memory device; a video signal line read from the memory device; a device for controlling said readout device to add or subtract lines for each field of line No. 1g, so that line No. 18 of the video signal read from said memory device constitutes the other of said video signal. It is something.

Such a mounting may require an encoder at the television output station to convert the normal video signal to a modified video signal prior to broadcast.
The octopus device converts the received modified bidet No. 1g into a VTR.
The decoder at the receiving 1d station can also be used for recording. However, is it possible to add a decoder like this? δ% Suke Station VC Oke/,)
VC has passed ^1 song too much because of Iiga.

In accordance with another aspect of the present invention, recording of the video signal line in response to a video signal that has been changed to 1 and 1 is prohibited while the video signal line is not recorded. There is provided an apparatus for compressing a video signal comprising a field of a video signal line to a sono-device, a memory device and a field of a video signal line in the apparatus, and a device for storing a video signal line from said memory device. A device for outputting the 1st line, and a reading device for adding and subtracting lines with respect to each field of the video 1st line read δr from the memory device.
lh # rereading and Karanashi.

The video signal lines read from the memory device thus form a modified video signal having varying field lengths.

Preferably, the memory device is operative to store digital signals, the storage device including a device for converting a video signal from an analog signal to a digital signal, and the reading device operable to read a digital signal from the memory device. The apparatus includes a device for converting the encoded digital signal into an all-analog 18'' signal and detecting the encoded video signal.

The control device is responsive to each stored memory address such as a device for storing memory addresses associated with storage areas in a vertically spaced memory device in a trough field of a video signal, and a device for selectively controlling a reading device. and a device for removing or rereading lines at the end of a previous field of a video signal stored in a memory device to produce a modified video signal.

The present invention is also adapted to a method for converting a 1C video signal to a 1C video signal, each of which consists of an input field consisting of a field of C1l capable of interfering with the analog video signal line. Convert the corrected video signal to an analog video signal with a field of constant width, convert this analog video direct line to a digital signal, and convert it to a memo+)-6
In order to record the digital signal in the memory, the digital signal line that was omitted to be recorded in the memory is read out from the memory device at a field speed of L-Y. , the conclusion - dismay 1. The process consists of converting the fy video signal into an M'lf analog video signal with a constant field length.

The present invention will be further understood by referring to the following description with reference to Figure 11. In Figure 1, a video signal from a program source 1o is modified by a video signal encoder 11, and the results thereof are shown in Figure 1. Blocked videos/issues and programs/
A TV transmission system is shown in which audio signals from sources are provided to a transmission system 12 for broadcast. The transmission path from the program source 10 to the transmission system 12 is also %1 to maintain the timing of the transmitted fV signal combined with the average timing of the corrected video signal. For example, a signal delay of 30 ms (duration of one television field)
It is also possible to include a delay device (not shown) to provide .

Broadcast signals are broadcast as shown via cable 13, but these signals can alternatively be provided by electromagnetic waves either directly or via a satellite link. As shown, the broadcast signal is optionally coupled via a conventional channel converter 14 to a conventional television receiver 15, which is reproduced in a manner well known in the art.

In the following, in detail, the video encoder 11 provides a large field length for the video encoder. The change in field X is as follows:
Television party fH■y! 15's 'l''Iiissue's calligraphy of the crotch has a love influence, and it is not light on the page, and on the page of 1 letter 'hanging', it is not a normal person, but 'listing'. This hinders h1 recording of the video signal in the video recorder.

FIG. 2 is a block diagram of the video/city code encoder 11 f:
I'm doing yF. The video input of the program source 10yj-ra is input to the input side of the timing device 201 and the analog/differential (Al1) converter via the low-pass filter 200 of the program source 10yj-ra. Sent to latch 202.

This A/D converter samples the analog video signal (/,) equal to four times the color subcarrier frequency Jb, which is supplied by the analog video signal (/,) and the sampling frequency J's VCν. Mark the valley sample on the latch 1. 8-bit digital number <lV
C convert linearly. As a result, color-subcarry 7) t47Bikl-j' b Ka3.5795451
For a 7Vi' SC video signal of VlHz, 991 dinotal samples of HIM are provided per water line.
3 and later read from it. The dinotal samples wQ from the memory device 203 are supplied to a latch and digital/analog converter 207 which operates at frequency ht8 to latch the dinotal 11IL provided thereto;
And convert these to analog video signals. This analog video No. 1G has a 42MEz low-pass filter and the output has been modified to exceed 1G of video output.
is filtered and ticketed δ in a (sinx)/Z equalizer, shown as block 208. It is supplied to the timing extraction table 207.

The timing extraction taste control 201 is shown a total of seven times earlier in FIG. Color burst Tsukuda appearance [i300i
Extract the color burst from the valley horizontal line η of the human-powered video signal and supply it to a color burst phase-locked loop (PLL) 301, and this loop FX
Play color burst cycle 1iJb. This is given for yet another PLL containing an oscillator with oscillations and +40j'bk.

The output is divided to produce a wave number of 15, which is shown in FIG. 3 and explained below.

This other PPL'J? and divider in a single block 30
2. The input video signal is also sent through the synchronous sensor 303.

It receives a composite synchronization signal from bidet No. 11 and triggers line counter 304i) to count the horizontal lines of the valley field. The output signal J', r' of the line counter 304, which is a logic high in each vertical interval, is divided by the field counter 305 to produce a signal OZE which changes the state of the valley field; corresponds to the phase of the color burst of the input video signal. Counters 304 and 305 are synchronized by a signal f generated in block 302 and shouldering 10 times the 7"L color subcarrier frequency μ.

Block 302 also includes: Already explained signal fs=4f
b and one frequency ft with a frequency of 1713, a signal fh with a horizontal line frequency, and a signal fh, which also has a horizontal line output, with a video (each horizontal line synchronization of m). 4H @ which becomes logical value 0 at 8 rus
IvG and Shao 1. Thus, the various timing signals have the following numbers of cycles. That is, f=35.79545Ml1Z f h=NG=i 5.734 j(fizJ'8
=14.31818 fj'=59.9+11zz
t=l, l o 14mHz O/E=29.97#
z FIG. 4 shows the memory device 203f in further detail. The device is configured as shown in one block 400 (1
104'l'TL6 with associated ECL for "2'L and TTL convergence for L'CL"
4 includes bit RAM (random access memory). This EAMtd is controlled and addressed polycyclically by address and control signals supplied by sub-control circuit 204 for loading and reading the deisotal video signal. Because of the relatively slow speed of each memory access cycle, digital video 18' is written and read from RAM 13 8-bit words at a time, and one bit of the valley word is written to and read from RAM 13 for 104 RAM valleys. read out or read out. Therefore, the signal f
The 8-bit video signal words from the A/D converter and latch 202 are transferred to the shift register 401 under the control of the 1g JtQ controller 202, and the words are transferred 13 at a time under the control of the
Each bit is transferred to the latch 402 and written as 1 to RAAi. On the other hand, the %8 bit word is the control circuit 20.
40 is read out from ltAM and stored 13 at a time in output latch 403, and loaded in parallel from latch 40 a y>1 into the shift register under the control of signal j8 and the modified memory 4i [203 Digital video output t-configure. The number of 13 words that are given priority to the RAM and will continue to be read out is selected based on the speed of the RAAi and the number of samples per horizontal line of the video signal of 910'+M, which is 70 times per horizontal line. This provides one extra memory access cycle.

Each 204 times the market is 45 times (as shown below). This ttilJ TiJ(2) path 204 is connected to the address selector 504 L' every valley memory access cycle.
From this, in order to select only two of the composition of the sub-increase signal and the address signal, a seven-ji:L I:I 55W counter 501,
It includes Pit 0111502 and latch 503-i. Counter 501 is clocked from signal jV to increment its count, and at every trough count, P is addressed from Q#502 to produce a set of 11 control signals, which control signal j°. It is latched by a latch 503 at the bottom.

The 1171J control signal in the j7 chip 503 is kAiμ(
block 400) and the periodic operation of the memory surface latch 403 and the 7Z space 50 that provides the RAM.
Controls the selection of the ★-included address or the indulgence address from the bus 06.

The incoming address on bus 505 is generated by a 16-bit synchronous counter 507 clocked by signal jL, so that the input video signal words are periodically written to successive memory locations. The read address on bus 506 is determined by adding an offset selected by selector 509 from launch 510 or latch 511 to the current increment address in modulo 216 adder 508, and adding this sum to signal ft. is generated by latching into latch 512 under the control of . The selector 509 receives the signal "Sh'L" generated on the Q output side of the D-type flip-flop 513.
This signal is also provided to microprocessor 514. Micron 0 Rosetsuza 514 Bakono Offsera) Q Latch 510 and 51Nr
Li and supply, load 16 of the match latch on turn 517
Under the control of the program, an address is given to the latch 515 via the common bus 516. The microprocessor also provides a signal to the data input g4D of the N/V-q flip-flop 513. Comparator 518 compares the read address on bus 506 with the bladder release address stored in latch 515 and, if the compared address is a clock, outputs the output signal gated by signal Jl at aAND gate 519. This produces a signal &Q which is applied to the clock input CK of flip-flop 513 as an interrupt signal to microprocessor 514. Microprocessor 514 also has latch 520
is given the starting address of the vertical interval from , which is present at the beginning of the vertical interval of the video transmission and is 1
This is a 1 address on bus 505 that is latched in latch 520 under the control of 100 FF.

Control circuit 204 also includes a random noise source 521 and a flip-flop 522. A random noise signal, such as the noise voltage of a diode or resistor comprising source 521, is clocked by signal j' h to the Q output of flip-flop 522, the output of which is coupled to microprocessor 514.

Control circuit 204 operates as follows. As previously discussed, the input video signal word is periodically convolved into memory and the starting address of the valley vertical interval is stored in latch 520.

The reading of video signal words from memory occurs approximately sequentially after some delay or offset, the amount of which is ramped up from one of latches 510 and 511 as determined by the signal [Sk;LrEC'l'. In this case, the selected offseter t4 generates an outgoing address in the incoming address. The valley offset amount is 70 times the number of fireflies,
Therefore, the total number of lines M f"i" are read out from the memory after loading the bidet No. 1g line into the memory, and b.

The starting address force of the vertical spacing of the valleys served from the latch 520 (further), 4 = As described in detail below, the microprocessor 514 sets the read address at which the offset is to be changed to one! 14] Set this address on line 5! 5. Take one breath and determine the appropriate offset and store it in one of the latches 510 and 511 not selected by selector 509 at the time.

The comparator 518 finally determines the correspondence between the current read address generated by the latch 512 and the new read address stored in the latch 515 by the memory update H'. In response, signal EQ goes to 1 and then goes back to 0 when the next leading edge of signal fl is applied to gate 519. This 1 to O transition state of the signal EQ triggers the free lag flop 513 via its clock input CK, transferring the logic level of the signal N/V at its D input to its Q output; This changes the cooking level of the signal 5hLh"CT1 and the previously unselected latch 510 or 51.
The offset iL stored at 1 is selected by selector 509. The transition state of No. 16 L and Q from 1 to O causes an interrupt to be sent to the microprocessor 514.

In response to this interrupt, microprocessor 5141r
i times number SI! ；L E Ci' in one state-
6 output, the new read address determined by this is given to the latch 515, and the signal N/V is sent to the signal S li; L
E Set the state to be the opposite of that of Ci'. The address latched by the latch 515 is then (') rjje, which is 4 times different from the output L address, and the comparator 518 (l no longer detects the female insect, and the 1-fl() , 1 maintain the state of 0.

Microprocessor 514td, bidet number 1- field length J9 [latch 510 and 5
11,000 sets) and the direct address for the latch 515. The direction of the field length trough change, ie, whether the field is shortened or lengthened, is determined by the output V of the free-ruff 0 flop 522. Changing the length of this field is done by not exposing the N, 1, for example, 2 or 4 lines of a given field, or by taking this n and putting out 1i7e, The first bidet fixed by this
Field t in number b is shortened by 2 or 4 lines, respectively, and extended by 8 or more. The incremental changes in the field length of the thus obtained modified video No. 1g are imposed by the memory size while maintaining the long-term average value of 525 television lines per frame. Within the constraints of
The conventional television reception of the television H image from No. 4, and the confinement by 1 pair, are unlikely to have any negative impact τ. As long as possible, the field length brings about the removal force or reversal of the line in the lower y1M part of the reproduced picture 1,
This (d) is not important and is usually not noticeable, as the normal television receiver/L: is overscanned by some lines, so it is not important and usually not noticeable. Changing field. In order to handle the unpleasant sottering of the 1IIJl image caused by the field length, the microprocessor 514 is configured to vary the field length relatively slowly.

Even if the length of one frame (two fields) is changed by two lines, there are at least two frames between such changes, or there is a negligible difference between them. The painting ends in a face that invites sottering. The good news is that the average value of the change in field intensity is typically no more than one line per three fields, so A
).

Regarding "Tsukuda Shin 11Lli 15th month of Showa 204", Tori 7J will also explain the flowchart shown in Fig. 6b' below. ■Eha, latch 510 K west - ox n
A signal 5ELk; CT=1 is tentatively added to use the offset sound to eliminate the anti-vibration field from the memory.

tIt's next time the 262-1/2 line is set, so the microbe 514 is the latch 515.
At the beginning, write the starting address in the vertical spacing of the latch 520 (as small as possible) and write this offset in the latch 511 so that it appears in the latch 510 &?ll'. Let's close the city.1ltc
, the microprocessor has already launched the output of flip-flop 522 and the signal O/L by scanning the starting address in the vertical interval of the next field from launch 520.
Let's try to resist the following. The latter signal ensures that the elimination of the line in the modified video line and the line does not destroy the phase sequence of the initial burst of color subcarriers that fall into the video line. Therefore, it is cut and given to the microprocessor 514.

If the output of flip-flop 522 indicates that the next field will be shorter than line 1Ii2, then the microprocessor sends a signal to latch 515 that straddles the two lines 1g as the next address. shorten the vertical interval start address of the next vertical interval by one decreased by the desired amount, and also shorten the vertical interval starting address of the next vertical interval by one decreased by the desired amount, and set the vertical interval starting address of the next vertical interval to 6 in latch 511 increased by an amount equal to two signal lines as the next offset to latch 510. i, determine the offset amount equal to the given offset ζ]. (-1) In contrast, if the output of flip-flop 522 indicates that the primary field is extended by, say, two lines, then the microprocessor selects one or more as the next address for latch 515. Determine the vertical direction of the field of the arrow 1i, I'1 and the closed iiH address, and set the next offset 1 to the latch 510 to set the two vertical arrows facing the vertical line to the latch 511.
Determine the offset blood equal to the offset written in 'l;KC'J.

When the current error output address reaches the vertical spacing start address in latch 515, comparator 518
establishes consistency and flip-flop register 513 is clocked to signal S E L I! according to signal N/V=o, which is now provided by microprocessor 514. ;
C'l' is changed to 0 and an interrupt to the microprocessor (block 600, FIG. 6) occurs. This new signal 5ELI! ;CT=0 causes selector 509 to select an offset from latch 511 to continue reading from memory;
Since it is equal to offset tj4t in 10, reading continues sequentially.

In response to this interrupt, the microprocessor
Indulge the RLH"CT (block 601) and determine its new state (block 602).

In this case, signal 5ELEC1''=O, and in response, microprocessor 514 sets signal N/V to 1 (signal Sb''Ll!; opposite to CT) at block 60.
3), then this fixed value of signal N/V, the determined offset amount for latch 510, and latch 515.
The address determined for is output to this latch (block 604).

Thereafter, block 60 sequentially outputs another vertically spaced starting address from latch 520 to microprocessor t.
5), also read signal 07E and the output of flip-flop 522. From this information.

As the microprocessor was already carried, 1 latch 511
The next offset pawl for and the next address judgment for latch 515 are added (block 606). For example,
If the next field is 262-1/2 lines of normal precision, the microprocessor will latch 51
Use the same offset values as in the latch 510 IC and the associated vertical 10'' starting address for latch 511. microprocessor 514
At this time, the next interrupt is sent to Samurai 1. message block 607).

In response, the aforementioned sequence is repeated for block 602. Signal ゛5ELJ! ;C1”h this time 1
Therefore, we approach block 608 in which the signal N/V is set to 0, and then in block 609 this signal N/V and the offset H determined for latch 511 and the address for latch 515 are set to these output to the latch, which leads to block 605. The above sequence is repeated as previously described.

From the above description, it can be seen that, for example, if the field is to be shortened by two lines, the con router 518 will establish consistency and the interrupt will occur two lines before the start of the next vertical 1uJ interval. It will be seen that as a result of switching selector 509, the offset is suddenly changed by two lines, so that the start-up is changed by this next vertical interval. Thus, the last two lines of this field are not read from memory. On the contrary, for example 2
For a field that expands to the line, the controller establishes consistency, the integration occurs at the beginning of the 1/2 vertical interval, and as a result of the switching of selector 509, the offset is at the arrow y. Since two lines are changed, two lines of field handling are read out from the memory before the readout is repeated vertically. The field length of the video signal modified in this way is 11M1
This can be done by removing a line from the end of each field, or by resizing the copied line to the small size of each field. As already mentioned, , such changes in field length, even if done gradually as mentioned above, are not noticeable in the normal playback and viewing of video signals in conventional television receivers; Its effect on a video signal with a full frame length prevents the recording of the video signal on the dependent video tape recorder.

FIG. 7 shows a modification of 4g1j, described above, which can be utilized when the television program source 7o, including the control and synchronization generator 71, is co-located with the security device. The decoding device consists of an open side j device 72 in this example. In this case, the television picture source is the program source 7oy.
>, this source may be, for example, a studio television camera or cine film, so that the aforementioned memory device 203 and associated conversion and latching circuitry can be omitted.

7, lilJ@I device 72 directly controls control and synchronization pulse generator 71 to provide the modified video signal on line 73 with the aforementioned variable field length. This control is achieved by directly controlling the video line counter of the device 71, and by controlling the running of the video line or the field by VC. The video signal on line 94 is directly from 1 to t2.

As mentioned above, a rolled video file cannot be recorded on a video tape recorder because it has a variable field length and frame length. Unlike the conventional witchcraft technique, which can be used at any cost without the usual horizontal interval, it is possible to record the video signal and impair the encoding operation. , Fukaki's revised video LC5 is not suitable for recording, but social news I/L cannot be changed. In fact, the decoder for converting the modified video signal into a form suitable for recording is substantially the same as the encoder shown in FIGS. I'm a baby girl
Don't say u. As mentioned above, the leather encoder P
Although the i-costs can be justified for television transmission systems, the comparable corporate costs of a single-use convenience decoder in a video tape recorder are generally considered prohibitive. It tends to be.

However, as shown in FIG. 8, in the block diagram, a low-pass filter 800 is configured by a square similar to the encoder configuration shown in Figure 21. Timing extraction device 4jJ
01. Possible configurations are shown, such as a decoder consisting of an A/D converter/latch 802, a circuit 803, a circuit 804, a latch/A converter 807, and a filter end equalizer 808. Furthermore, this decoder is controlled by a control circuit 804 to control the video return erasure level to the device 807, and includes a selector 8 for directly switching lines removed from the stop video signal.
06 [Includes] As shown in the figure, the control circuit @ 804 receives the synchronization number 16 from the timing extraction device 801, and from this, the control circuit il''j, 1 and the removed board '4 in Ivy on the line [busy dog chatter].

From the above description of the method used by the encoder, the Department has: Detailed configuration of a decoder for producing a rapid video signal from a static video signal. It will be clear.

I wrote about Fukaki's 'Niwa's Yase Aku-sama in Review 1, but the total was 1 α1. (Many modifications and applications may be made without departing from the scope of the invention set forth in the scope of this article.)
It's in the eyes.

[Brief explanation of drawings]

FIG.
V transmission 4@system 7f: block diagram, Fig. 2. A block diagram (not shown) of a video signal encoder τ including a beam/rming device, a memory display, and a control circuit. FIG. 5 is a block diagram of a control circuit on the same sheet as FIG. 1 and shows a block diagram of a memory device. FIG. 6 is a flowchart showing the operation of the control circuit. FIG. 7 is a block diagram illustrating a simplified form of a video signal encoder, particularly for use when a TV program source is co-located with the encoder. and FIG. 8 is a block diagram illustrating a video signal decoder provided to decode the modified video signal and enable its recording. DESCRIPTION OF SYMBOLS 10... Program source, 11... Video signal encoder, 12... Transmission system, 13... Cable, 14... Channel converter, 15... Television reception, 70... Television program source, 71...Control and synchronization pulse generator, 72...11J XI M location, 73-' --I
P! l@7'3,200--filter, 201...
Timing extraction device, 202...A/D converter and clutch 03.../Memory device, 204...
・City 1] 11 mark circuit, 207...Digital/analog converter and latch, 208...Filter and equalizer, 300...Color burst extraction device, 3
01...Color burst phase locked loop, 302...
... PLL and frequency divider, 304... line counter,
305...Field counter, 400...II
CL/'2'i' L converter Miyabi RAM, 401
．． 404...Shift register, 402.403...
Latch, 500, 504...address selector. 501...Counter, 502...P k OM. 503... Latch, 505.506... Bus, 50
7...Synchronization counter, 508...Dictionary device t509
...Selector, 510.511.512.515%
520... Latch, 513... Fritz flop,
514・Salary・Microprocessor, 516...Common path, 517...Line, 518...-Comparator, 5
19...AND dirt, 521...noise source, 522...flip frog. Patent Issuer Northern Telecom Limited Figure 2 Figure 3

Claims (1)

Claims: 1. A method for modifying a video signal to inhibit recording of the video signal while permitting a television receiver to display a video image in response to the modified video signal, comprising:
A method comprising changing the field length of a video signal to produce a modified video signal. 2. The method of claim 1, wherein the field length of the video signal is changed by removing and appending the video line from the end of each field of the video signal. . & A method according to claim 2, wherein the step of adding video lines to Wl of each field of said video signal is repeating the lines of said field. 4. The field length of the bidet No. 148 is increased by one line per three fields + at a proportion that is not uniformly large. Method. 5. The field length of the video signal is changed such that the long-term average value of the field quality of the modified video signal is equal to the field length of the unmodified signal. - The method according to any one of it. 6. The step of changing the field length of the video signal includes the step of storing video signal lines of the video signal to be IIIRK modified in a memory, the video lines being read out substantially sequentially. 2. A method as claimed in claim 1, in which this line is removed from the F range of the individual fields and read out to produce respectively shortened and g lengthened fields in modified bidet No. 15. 7. An apparatus for converting between a video signal comprising a field of constant length of a video signal line and a modified video signal comprising a field of variable length of a video signal line, comprising: a memory device; and said memory device. a device for storing one video signal line of said video signal in said memory device; a device for reading a video signal line from said memory device; and a device for controlling the readout device to add video lines thereto, thereby ensuring that the video signal lines read from the memory device constitute another of the video signals. Featured device. &Television 1 year old receives video l[!] in response to a modified video signal. 2. In an apparatus for modifying a video signal comprising a field of video signal lines to inhibit recording of the video signal during a trough of bubbling an image, the memory device and the video signal line of the video signal line No. A device that stores data in a memory device. an apparatus for reading the video signal lines from the memory; and an apparatus for controlling the reading apparatus to remove and add video lines from and to individual fields of the video signal lines read from the memory device. 15. An apparatus characterized in that the video signal line read from the memory device forms a modified video having a varying field length. 9. The memory device operates to store a digital signal, the storage device is a device for converting the video signal from an analog signal to a digital signal, and the reading device stores the digital signal ΦC output from the memory device.
9. Apparatus according to claim 8, characterized in that the apparatus converts the video signal into an analog signal to form a modified video signal. 10.1iiii. The control device is configured to store memory addresses associated with storage in a memory device of vertical spacing in a valley field of the video signal, and in response to each stored memory address, the readout device; and a device for selectively controlling the video signal and removing or rereading the video line at the end of a previous field of the video signal stored in the memory device to generate a modified video signal. Claim No. 8
The table page listed in Section 9 or Deception Section 9. 11. In a method for converting a modified video signal with a convertible length field of an analog video signal line into an analog video signal of a constant field length, the 191E12 analog video signal line No. 1 Convert the external digital signal to digital data and record the external digital signal directly on the memory surface.1. However, by removing the digital signal line from the digital signal that has been directly memorized, or by adding the Daisymel line to it, the memory can be stored at a constant field ratio. A method comprising the steps of issuing a digital signal 'C#' from a device and converting the resulting digital signal into the aforementioned analog video signal of a constant field length.