JPS595626A - Forming method of electrode wiring - Google Patents
Forming method of electrode wiringInfo
- Publication number
- JPS595626A JPS595626A JP11485582A JP11485582A JPS595626A JP S595626 A JPS595626 A JP S595626A JP 11485582 A JP11485582 A JP 11485582A JP 11485582 A JP11485582 A JP 11485582A JP S595626 A JPS595626 A JP S595626A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- thickness
- layer
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は金属の電極配線形成法に関するものである。[Detailed description of the invention] The present invention relates to a method for forming metal electrode wiring.
半導体の集積化が進むにつれて多層配線が多用されてい
る。第１図にアルミニウム（Ａ７１１）層を用いた２層
配線の断面図を示す。同図において、１は半導体基板、
２は第１層のＡｌ電極配線、３は絶縁膜、４は第２層の
Ａ４電極配線である。この場合、第１層のｋｌ膜２によ
り生じる段差のために第２層のｋｌ膜４は段差部で線切
れを起しやすい。この為、第１層のｋｌ膜２をテーパ状
に形成するなどの工夫もされているが、微細加工性を考
えると問題があり、多層配線に適した電極配線膜の新し
い形成法が望まれていた。As semiconductor integration progresses, multilayer interconnections are increasingly used. FIG. 1 shows a cross-sectional view of a two-layer wiring using an aluminum (A711) layer. In the figure, 1 is a semiconductor substrate;
Reference numeral 2 denotes an Al electrode wiring of the first layer, 3 an insulating film, and 4 an A4 electrode wiring of the second layer. In this case, because of the step difference caused by the first layer KL film 2, the second layer KL film 4 is likely to break at the step portion. For this reason, attempts have been made to form the first layer KL film 2 in a tapered shape, but this poses a problem when considering microfabrication, and a new method for forming an electrode wiring film suitable for multilayer wiring is desired. was.
本発明はこれらの問題点を解決するもので、本発明は、
絶縁膜をスペーサとして金属を蒸着、リフトオフして電
極配線膜を形成した後、絶縁膜の表面の一部をエツチン
グにより除去して薄層化し、絶縁膜と金属膜との厚さの
差を低減化、とりわけ、０．３μｍ以内にすることによ
り第２層配線の線切れをなくすことができる電極配線形
成方法を提供せんとするものである。The present invention solves these problems.
After depositing metal using the insulating film as a spacer and lifting off to form an electrode wiring film, a part of the surface of the insulating film is removed by etching to reduce the thickness of the insulating film and the metal film. In particular, it is an object of the present invention to provide a method for forming an electrode wiring that can eliminate line breaks in the second layer wiring by making the thickness within 0.3 μm.
以下に本発明の実施例について説明する。第２図に本発
明の実施例を示す。まず、半導体基板１上に１．６μｍ
の厚さの５ｉＯｚ膜５を形成し、厚さ２μｔｎのホトレ
ジスト６を塗布し、所定パターンを形成する。ホトレジ
スト６をマスクとしてドライエツチングを行うことによ
り、５ｉ０２膜６に所定開口部が形成され、また、ホト
レジスト６も、その表面層がエツチングされて薄層化し
て、その一部が残存する（第２図（ａ））。次に、ｋｌ
金属を０．７μｍの厚さで蒸着し、前記ホトレジスト膜
６と共にリフトオンすることにより金属膜７を開口部内
に形成する（第２図（ｂ））。ここで、本実施例ではリ
フトオフを用いるので微細な電極形成が可能となる。最
後に、塩素を含−１ないフレオン系のガスを用いて５ｉ
０２膜６をエツチングして金属膜子とほぼ同じ厚さにす
る（第２図（Ｃ））。この場合。Examples of the present invention will be described below. FIG. 2 shows an embodiment of the present invention. First, a 1.6 μm thick film was applied on the semiconductor substrate 1.
A 5 iOz film 5 having a thickness of 2 .mu.tn is formed, and a photoresist 6 having a thickness of 2 .mu.tn is applied to form a predetermined pattern. By performing dry etching using the photoresist 6 as a mask, a predetermined opening is formed in the 5i02 film 6, and the surface layer of the photoresist 6 is also etched to become a thin layer, with a portion remaining (second Figure (a)). Next, kl
A metal film 7 is formed in the opening by depositing a metal to a thickness of 0.7 μm and lifting it on together with the photoresist film 6 (FIG. 2(b)). Here, since lift-off is used in this embodiment, fine electrode formation is possible. Finally, using Freon-based gas that does not contain chlorine, 5i
The 02 film 6 is etched to have approximately the same thickness as the metal film element (FIG. 2(C)). in this case.
塩素を含まないフレオン系のガスではＡｌはエツチング
されないので、第２図（Ｃ）では、段差のない平担な面
が実現されている。次に、絶縁膜を形成し第２層のＡ４
電極を形成した場合でも段差がないので、第２層ｋｌ電
極の線切れがない。Since Al is not etched with Freon-based gas that does not contain chlorine, a flat surface with no steps is achieved in FIG. 2(C). Next, an insulating film is formed and a second layer of A4
Even when electrodes are formed, there are no steps, so there is no line breakage in the second layer kl electrode.
ことで、絶縁膜６と金属膜７との厚さの差は０．３μｍ
以内にする必要がある。Therefore, the difference in thickness between the insulating film 6 and the metal film 7 is 0.3 μm.
Must be within.
金属膜７の高さｈｋｌを０．７μｍに固定し、エツチン
グ後の絶縁膜６の厚さｈｉを０．７μｍ 、 １μｍ。The height hkl of the metal film 7 is fixed at 0.7 μm, and the thickness hi of the insulating film 6 after etching is 0.7 μm and 1 μm.
１．３μｍと変化させ、その上にプラズマＣＶＤで厚さ
０．５μｍの窒化膜を形成した。さらに、第１層のｋｅ
電極配線と直角方向に線幅０．５μｍの第２層ｋｌ電極
配線を厚さ０．７μｍで形成した。その場合、第２層配
線の線切れは、 ｈｉ＝＝１．３μ舟のとき２．４％、
ｈｉ＝１μｍのとき０．０５％、 ｈｉ＝０．７μｍの
とき０％である。この’ｌ結果を図示すると、第３図の
ようになる。すなわち、絶縁膜と金属膜の厚さの差を０
．３μｍ以内にすれば線切れはほとんどないことが理解
される。The thickness was changed to 1.3 μm, and a nitride film with a thickness of 0.5 μm was formed thereon by plasma CVD. Furthermore, the ke of the first layer
A second layer kl electrode wiring having a line width of 0.5 μm and a thickness of 0.7 μm was formed in a direction perpendicular to the electrode wiring. In that case, the line breakage in the second layer wiring is 2.4% when hi==1.3μ,
When hi=1 μm, it is 0.05%, and when hi=0.7 μm, it is 0%. This 'l result is illustrated in FIG. 3. In other words, the difference in thickness between the insulating film and the metal film is 0.
．． It is understood that if the thickness is within 3 μm, there will be almost no line breakage.
なお、上記実施例では、リフトオフに用いるスペーサと
なる絶縁膜５としてＳｉＯ２膜について説明したが、Ｓ
ｉ３Ｎ４膜などの他の絶縁膜でもよい。In the above embodiment, the SiO2 film was explained as the insulating film 5 which becomes the spacer used for lift-off, but the SiO2 film
Other insulating films such as an i3N4 film may also be used.
またポリイミドなど有機絶縁膜も使用可能であるが、こ
の場合は０２プラズマでエツチングを行う必要がある。It is also possible to use an organic insulating film such as polyimide, but in this case it is necessary to perform etching with 02 plasma.
更に、パターン形成については、ｊｆｆｉ常のレジスト
を用いた場合を述べたが、多層レジスト法を用いること
もできる。Furthermore, regarding pattern formation, although the case where a regular resist is used has been described, a multilayer resist method can also be used.
以上に述べたように、本発明によれば、絶縁膜をスペー
サとして金属を蒸着、リフトオフして電極を形成した後
、ドライエツチングにより絶縁膜の一部を除去して、絶
縁膜を薄膜化することによりこの上に絶縁膜を介在させ
て形成される第２層配線の線切れをなくすことができる
。As described above, according to the present invention, a metal is vapor deposited using an insulating film as a spacer, lift-off is performed to form an electrode, and then a part of the insulating film is removed by dry etching to reduce the thickness of the insulating film. This makes it possible to eliminate line breaks in the second layer wiring formed with an insulating film interposed thereon.
膜と金属膜の厚さの差に対する線切れを示す特性図であ
る。
１・・・・・・半導体基板、２・・・・・・第１層のＡ
／電極配線膜、３・・・・・・絶縁膜、４・・・・・・
第２層のｋｌ膜、６・・・・・・酸化膜、６・・・・・
・ホトレジスト、７・・・・・・金属電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図
第３図
θ
（ｉＡ−ＩＡＩ））ｔ１２＝FIG. 3 is a characteristic diagram showing line breakage with respect to the difference in thickness between a film and a metal film. 1... Semiconductor substrate, 2... First layer A
/electrode wiring film, 3...insulating film, 4...
Second layer kl film, 6...Oxide film, 6...
- Photoresist, 7... Metal electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 θ (iA-IAI))t12=
Claims (2)
縁膜上に所定パターンの被膜を被着して、前記被膜をマ
スクとして前記絶縁膜に開口部を形成する工程と、全面
に金属膜を形成した後、前記被膜を除去して前記開口部
に前記金属膜を残存させる工程と、前記絶縁膜の表面の
一部をエツチング除去して前記絶縁膜と前記金属膜との
厚さの差を低減する工程を含むことを特徴とする電極配
線形成方法。(1) A step of forming an insulating film on a semiconductor substrate, a step of depositing a film in a predetermined pattern on the insulating film, and forming an opening in the insulating film using the film as a mask, and a step of forming an opening in the insulating film on the entire surface. After forming the film, there is a step of removing the film to leave the metal film in the opening, and etching away a part of the surface of the insulating film to reduce the thickness of the insulating film and the metal film. An electrode wiring forming method characterized by including a step of reducing the difference.
なすエツチング除去を含むことを特徴とする特許請求の
範囲第１項に記載の電極配線形成方法。(2) The electrode wiring forming method according to claim 1, which includes etching removal to reduce the difference in thickness between the insulating film and the metal film to 0.3 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11485582A JPS595626A (en) | 1982-07-01 | 1982-07-01 | Forming method of electrode wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11485582A JPS595626A (en) | 1982-07-01 | 1982-07-01 | Forming method of electrode wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS595626A true JPS595626A (en) | 1984-01-12 |
Family
ID=14648382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11485582A Pending JPS595626A (en) | 1982-07-01 | 1982-07-01 | Forming method of electrode wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS595626A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51113478A (en) * | 1975-03-28 | 1976-10-06 | Fujitsu Ltd | The manufacturing method of semiconductor device |
| JPS5240968A (en) * | 1975-09-29 | 1977-03-30 | Toshiba Corp | Process for production of semiconductor device |
-
1982
- 1982-07-01 JP JP11485582A patent/JPS595626A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51113478A (en) * | 1975-03-28 | 1976-10-06 | Fujitsu Ltd | The manufacturing method of semiconductor device |
| JPS5240968A (en) * | 1975-09-29 | 1977-03-30 | Toshiba Corp | Process for production of semiconductor device |
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