JPS5951074B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large-capacity dynamic semiconductor memory device, and aims to effectively utilize the chip area by devising a method of arranging column decoders for selecting sense amplifier outputs.

MOS dynamic RAM, which consists of one transistor, one capacitor type memory cells arranged in a matrix, has a capacity of about 4 bits and 16 bits.
As shown in FIG. 1, sense amplifiers 5A, .

It is possible to divide them into two groups and arrange them. The example shown in the figure is an example of a memory with a capacity of nxm bits, and cell group C
G,,CG. has nXm/2 cells. Cell group C
m/2 row address lines (word lines or low lines) RL selected by the row decoder RD run horizontally in G, and one of the input/output terminals of the sense amplifiers 5A1 to 5An. The n connected digit lines DG run in the vertical direction. A memory cell MC is provided at each of these intersections. Second cell group CG. Similarly, the n digit lines drawn out in the vertical direction from the other of the pair of input/output terminals of the sense amplifiers 5A to 5An are designated by the symbol DG. Cell group CG,,CG. A dummy word line DRL is provided for each of the digit lines DG, and dummy cells DC are provided at the intersections of this dummy word line DRL and each digit line DG, DG. Although FIG. 1 depicts only one of these cells MC and DC as a representative, for example, the first cell group CG,
When the real cell MC is selected in the second cell group CG. Then, the dummy cell connected to the digit line DG that is paired with the digit line DG of the cell is selected, so the first
MC and DC in the figure indicate both real and dummy cells that are read simultaneously. Although not shown, a data bus is provided on both sides of the sense amplifier row, and the sense amplifier output is taken out through the bus.
, DG, and therefore the sense amplifier SAi (i is 1,
2...n) is made in the column decoder. In order to maintain the symmetry of the sense amplifier circuit, this column decoder is divided into a 1/2 column decoder on the line DG side and a 1/2 column decoder on the line DG side, as shown in FIG. Figure 2 specifically shows the main parts of Figure 1.
The memory cell MC consists of a MOS transistor Q that is turned on when the word line RL is selected and becomes the JH level, and a capacitor Cs provided on the source side of the MOS transistor Q.

Dummy cell DC selects dummy word line DRL and goes high.
A transistor Q,' that is turned on when the level is reached, and a capacitor iCS' whose capacitance value is approximately 1/2 of the capacitor Cs'.
A transistor Q performs reset by discharging the charge of the capacitor Cs' before a read operation. (turns on with reset signal RST). Reading out information from cell MC is well known and begins by precharging digit lines DG and DG. Then, when word lines RL and DRL are selected by the row decoder, transistors Q, ,Q,' of cells MC and DC are all turned on, and capacitances Cs and C are turned on.
s' is connected to digital lines DG, DG'. Since the capacitance Cs' of the dummy cell DC has been discharged in advance, the potential of the digital line DG is slightly lowered by this connection. On the other hand, on the real cell MC side, if the capacitor Cs is not charged ('0'' written), the potential of the digital line DG is D.
(Since Cs>Cs'), the potential of the digital line DG remains unchanged when it is charged (``1'' writing) (the precharge voltage of DG and the voltage of Cs are same). The sense amplifier SA detects and amplifies this minute potential difference between DG and DG.
The amplified outputs appear on the same digital lines DG, DG, but the potential difference has increased. Then transistor Q by column decoder CD. , Q, are turned on, the digital lines DG, DG are connected to the data bus lines BUS, BUS, and the level of the bus becomes that of DG, DG. The input/output amplifier IOA further amplifies the levels of the buses BUS and BUS to produce the readout output DOut of the cell MC. D,
N is the input data at the time of writing, D, NC7) H, L
The levels of the buses BUS and BUS are set to H, L, or vice versa, and the levels of the digital lines DG and DG are also set in the same manner. , Q, and further Q, charge or write to the capacitance Cs of the cell MC. The column decoder CD shown in FIG. 2 is connected to each sense amplifier. S.A.
corresponds to n sense amplifiers S as shown in Figure 1.
If A,,SAn are provided, the same number of column decoders C
D are arranged along the sense amplifier row.

For example, if m = n = 128 in a 16K bit RAM, the number of sense amplifiers SA will be 128. The same number of column decoders CD, 128, are provided.
By the way, if the Mxn bit memory cells are simply divided into two on both sides of the sense amplifier as shown in Figure 1, m/2 cells will be connected to one side of each sense amplifier SA, so m
With the increase in digital lines. DG and DG become longer, and their stray capacitance CDG increases. In a dynamic memory, cell information is read out as described above, so when CDG becomes large, level changes in DG and DG become small, making reading difficult. That is, assuming that the precharge voltage of the digit line DG is Vd and the memory cell MC is not charged, the level change ΔVSIG of the digit line due to Q1 being turned on is as follows.

The ratio of Cs and CDG CDG/CS is generally the C ratio (γ)
When this is used, equation (l) becomes as follows.
The differential input of the sense amplifier SA is ΔV. on the line DG side. ，
G and ΔV on the line DG side. , G, the capacity of the dummy cell is set to 1/2 of the capacity of the real cell.

Generally, Vd=3V and about γ-10 to 15, so for example, if γ+1=10, the sense amplifier input becomes 150 mV from equation (3). In a normal sense amplifier, the lower limit of the input level is about 100 mV, so if γ=10 to 15, it can be detected sufficiently. However, this condition is satisfied by m≦128, and 16K bit RAM, . m=n
= 128, there is no particular disadvantage, but as the capacity of RAM increases, for example to 256K bits, m = n = 512 in the square configuration shown in Figure 1, and therefore m/2 = 25.
6, CDG increases and becomes γ'': about .40 to 60. Therefore, the value of equation (3) is expected to be several tens of mV, which will lead to a situation where the sense amplifier SA cannot detect it. Therefore, instead of using a square matrix of m2n, the row address line RL is lengthened to increase the number of cells arranged along this line, and the number of cells arranged along the digit line is reduced, that is, n>m. Then, 256K
It is possible to configure RAM with bits or more.

For example, for 256K bits, n: 1024, m=
256 or n:2048, and m=128, the above problem can be avoided. However, if you do this, R
Due to the planar pattern of the AM, the chip is rectangular, making it difficult to mount it in a normal package that is intended to be square, and also having problems with mechanical strength, such as being easily divided into two in the longitudinal direction. The memory structure of FIG. 3 or 4 attempts to solve this problem by keeping the number of memory cells arranged along the digit line to a small number while allowing for a nearly square memory area.

That is, in FIG. 3, the cell of Nxm bits is divided into four cell groups CGl to CG4 of Nxm/4 bits each, and in FIG.
A sense amplifier and a column decoder group are arranged between each group. In this way, even with a 256K bit RAM, m/4 = 128 in the case of Fig. 3, and m/8 = 64 in the case of Fig. 4, so the C ratio γ can be suppressed to 10 to 15. Therefore, the first and second cell groups CGl,
Sense amplifier groups SA provided between CG2 and between the third and fourth cell groups CG3 and CG4, respectively.
Even if the input limit of Gl, SAG2, . . . is about 100 m, optical cell information can be sensed. However, if the column decoder groups CDGl, CDG2, . . . are provided on both sides of the sense amplifier strings SAGl, SAG2, . occurs. This will be explained with reference to FIG.

This figure specifically shows the main part of FIG. 3, and m/2 row address lines RLl to RLm/2 (one is a dummy) are shown in the first cell group CGl (the same goes for the others). Derived laterally from a row decoder not shown. Then, the digit lines [, [, .
A /2-bit cell MC (including a dummy) is provided.
A second cell group CG2 having the same configuration is also provided on the other end side of the first sense amplifier group SAGl, and 1-bit cell information selected from the cell groups CGl and CG2 is transmitted to the bus line BUSl,
It is taken out on BUS1. The lower half consisting of the third cell group CG3, the second sense amplifier group SAG2, and the fourth cell group CG4 has the same configuration as the upper half, and the cell groups CG3, CG4
The 1-bit cell information selected from the bus line BUS
2, taken out on BUS2. As mentioned above, for the first sense amplifier group SAG1 consisting of sense amplifiers SAl, SA2, . . .
A first column decoder group CDGl consisting of 2, . . . is provided, and sense amplifiers SA/, SA2'', .
A second column decoder group CDG2 consisting of column decoders CDl'', CD2'', . . . is provided for a second sense amplifier group SAG2 consisting of . Incidentally, the sense amplifier SAl selected by the column decoder CDl and the sense amplifier SA/ selected by the column decoder CDl'', and thus the digit line T5C;7,DG,,Dα7,DG1'' belong to the same column on the m×n matrix. Therefore, although the first column decoder group CDGl and the second column decoder group CDG2 have exactly the same function, it is necessary to arrange a plurality of column decoder groups due to layout design problems. For this reason, the chip area cannot be effectively used for memory cells, and a large portion of the chip area is occupied by sense amplifiers and decoders. For example, in the memory format shown in Figure 1, it is possible to allocate about 50% of the chip area to the memory cell group, but in the formats shown in Figures 3 or 4, this drops to 40% or even 30%. . Furthermore, since the number of column decoders driven by the column address buffer is large, there are also drawbacks such as a problem of speed reduction due to an increase in load capacity. The present invention aims to improve these points,
In a semiconductor memory device in which a plurality of blocks having a sense amplifier column and a dynamic memory cell group connected to the sense amplifier column are arranged in parallel, and a row decoder is provided corresponding to the plurality of blocks, the sense amplifier of each block is arranged in parallel. The present invention is characterized in that a column decoder for selectively outputting the outputs of the blocks to the data bus is commonly provided to the plurality of blocks, and this will be explained in detail below with reference to the illustrated embodiment.

FIG. 6 is a schematic diagram showing one embodiment of the present invention, and FIG. '7 shows a specific example thereof.

This example uses Nxm bits (especially n
= m) is divided into four parts, and the same parts are given the same reference numerals. The difference between this example and FIGS. 3 and 5 is that a column decoder group is no longer provided for each sense amplifier group SAG1, SAG2, and a single column decoder group CDG is commonly provided for these groups. , a point provided parallel to the sense amplifier group outside the area of the sense amplifier group and memory cell group (not necessarily provided on one side edge, but parallel to the sense amplifier group at the center θ that divides the plurality of sense amplifier groups into two) ), and column select lines (column address lines) CLl, CL2, . . . from each column decoder CDl, CD2 . . . in the column decoder group CDG.
... is pulled out and passed through the area, and the sense amplifier group SA
The point is that sense amplifiers (for example, SA, , SA,') belonging to the same column of Gl and SAG2 are selected at the same time. Lines CL, CL due to element structure. , ・ ・ ・
. . . is a multiple wiring that passes through the upper part of the cell formation region, and connects each transistor Q in the same column. ,Q
, connect to the gate of . In this way, the number of column decoders does not increase as the number of sense amplifiers increases and therefore the number of cell divisions increases, so the chip area can be reduced more effectively than in Figures 3 and 4. or reduce the required area. Further, since the size of each memory cell can be increased by keeping the chip area constant, the logic amplitude can be increased by increasing the capacitance Cs, which facilitates the design of the sense amplifier. Furthermore, since the load seen from the address buffer is one column decoder group, the load capacitance is reduced and high-speed operation is expected. Incidentally, in the present invention, since the sense amplifiers in the same column, for example, SAI and SAI', are selected at the same time, the bus lines BUS, BUSI and BUS. ，
Outputs appear simultaneously on BUS2, but these can be easily separated by providing a bus decoder in the subsequent stage, specifically in the row decoder section. For example, in the case of four divisions in Figure 6, (
The row decoder is operated with the row address of N-l) bits, and the bus decoder is operated with the remaining 1 bit (2N=
When m=n, the column address operates the column decoder with N bits). In the embodiment, the case where the image is divided into four is taken as an example, but it is clear that the present invention can be applied to cases where the image is divided into eight as in FIG. 4 and other cases. As described above, according to the present invention, when a large number of cells of a MOS dynamic RAM are divided into four or more cell groups for selection, only one column decoder group is required, so the capacity of the RAM can be particularly increased. The effect becomes more pronounced as time goes on.

[Brief explanation of drawings]

Figure 1 is a schematic configuration diagram of a general MOS dynamic RAM, Figure 2 is a circuit diagram of the main part of Figure 1, and Figures 3 and 4 are conventional MOS dynamic RAMs that divide a large number of cells into four or more cell groups. M.O.S.
A schematic configuration diagram of a dynamic RAM, FIG. 5 is a circuit diagram of the main part of FIG. 3, FIG. 6 is a schematic diagram showing an embodiment of the present invention, and FIG. 7 is a circuit diagram of the main part of FIG. 6. . In the figure, MC is a dynamic memory cell, CGI to CG
.

Claims (1)

[Claims] 1. In a semiconductor memory device in which a plurality of blocks having a sense amplifier column and a dynamic memory cell group connected to the sense amplifier column are arranged in parallel, and a row decoder is provided corresponding to the plurality of blocks, the sense amplifier of each block is A semiconductor memory device characterized in that a column decoder for selectively outputting an output of an amplifier to a data bus is provided in common to the plurality of blocks.