JPS5950224B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device which is equipped with a substrate bias generation circuit and which suppresses the injection of minority carriers into a semiconductor substrate.

A MOS type integrated circuit is provided with a substrate bias generation circuit that applies a bias to a semiconductor substrate to control a threshold voltage.

For example, as shown in FIG. 1, this substrate bias generation circuit is composed of MOS transistors Q1 and Q2, a diode D, a capacitor Cl, and an oscillator OSC, and applies a bias to the semiconductor substrate S, where C2 represents a stray capacitance. . When point a of the output of the oscillator OSC becomes high level,
The potential at point b increases via capacitor Cl, and transistor Q1 is turned on. Thereby, the oscillator O
When the potential at the point a of the SC output was at a low level in the previous cycle, the charges that flowed from the semiconductor substrate S through the point c, the diode D, and the transistor Q2 are discharged to the ground side through the transistor Q1. Furthermore, when the output point a of the oscillator OSC becomes a low level, the transistor Q1 is turned off because the point b has a negative potential with respect to the ground, and this negative potential flows from the point c to the semiconductor substrate S via the diode D and the transistor Q2. A negative bias voltage is applied to the When a substrate bias generation circuit as described above is provided on a semiconductor substrate on which memory elements, logic elements, etc. are formed, a potential state occurs in which the junction formed between point b and the semiconductor substrate is in the forward direction. In this case, injection of minority carriers into the semiconductor substrate occurs.

These minority carriers have an adverse effect on nodes in dynamically operating parts and nodes with high impedance. The present invention is equipped with the substrate bias generation circuit as described above, thereby suppressing the injection of minority carriers into the semiconductor substrate, and absorbing the injected minority carriers. The purpose of this is to prevent the negative influence i caused by minority carriers on other circuit parts of the circuit.

Examples will be described in detail below. FIG. 2 is an explanatory diagram of an embodiment of the present invention, in which 1 is a p-type semiconductor substrate, 2 is a metal surface such as a heat sink on which the semiconductor substrate 1 is mounted, and 3 is an explanatory diagram of an embodiment of the present invention.
, 4, 5 are n-type regions, 6, 7 are gate electrodes,
The circuit configuration that is the same as that shown in Figure 1 is capacitor C.
1. It is formed together with the oscillator OSC.

That is, the transistor Q1 has a source region 3 and a drain region 4.
and a gate electrode 6, and the transistor Q2 is composed of a source region 4, a drain region 5, and a gate electrode 7, and the region 4 is shared by the transistors Ql and Q2. As mentioned above, the transistor Q1 turns on and off according to the output of the oscillator 0SC, and the terminal b of the capacitor C1
The point becomes a repeating ground potential and negative potential.

When point b is at a negative potential, the p-type semiconductor substrate 1 and the n-type region 4 are in a forward potential state, and minority carriers are injected into the semiconductor substrate 1. Most of these minority carriers become the substrate current 1BB, and the other part becomes the bias voltage V. 0 and the power supply voltage Ss, and the remainder flows into the memory element and the high impedance node, causing malfunction. Therefore, in the present invention, at least the semiconductor substrate portion 8 immediately below the region 4 is made into a p-type high concentration region.

Thereby, the injection rate of minority carriers is reduced, suppressing the injection of minority carriers into the semiconductor substrate 1 when the junction 2 between the region 4 and the semiconductor substrate 1 is in a forward potential state, and dynamically increasing the number of minority carriers. It is possible to prevent minority carriers from flowing into memory elements or high impedance nodes that perform operations. Further, regions 9 and 10 of the opposite conductivity type to the semiconductor substrate 1 are formed around the transistors Ql and Q2, and the regions 9 and 10 are grounded as shown in the figure or an appropriate bias voltage is applied thereto. Minority carriers diffused into the substrate 1 can be absorbed.

That is, it absorbs minority carriers that tend to flow into nodes of circuits that perform dynamic operations or nodes of high impedance. As described above, the present invention provides the high concentration region 8 directly below the region 4 where the junction with the semiconductor substrate 1 of the substrate bias generation circuit is in a forward potential state, and the opposite region of the semiconductor substrate 1 surrounding the substrate bias generation circuit. By forming the high concentration region 8, the injection of minority carriers from the region 4 into the semiconductor substrate 1 is suppressed.
10 can absorb the minority carriers diffused into the semiconductor substrate 1, thereby preventing the minority carriers from flowing into nodes performing dynamic operation or high impedance nodes and having an adverse effect on memory operation or logic operation. can be prevented.

In that case, it is possible to prevent the negative influence of minority carriers on either the high concentration region 8 or the regions 9 and 10.
If both are formed, the effect will be even greater. In the present invention as described above, the p-type high concentration region 8 formed in contact with the n-type region 4 can be formed all over the surrounding area of the n-type region 4; 8 is transistor Q
If it extends below the gate electrodes 6 and 7 of the transistors Ql and Q2, it is undesirable because it increases the threshold value (Th) of the transistors Ql and Q2. The n-type region 4 is the capacitor C1.
In order to increase the n
A p-type high concentration region may be formed all over the periphery of the type region.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of a substrate bias generation circuit, and FIG. 2 is an explanatory diagram of an embodiment of the present invention. 0SC is an oscillator, Ql, Q2 are MOS transistors, C
1 is a capacitor, D is a diode, 1 is a semiconductor substrate, 2
is the metal surface, 3, 4, 5 are the sources of the MOS transistors,
A drain region, 6 and 7 are gate electrodes, 8 is a high concentration region, and 9 and 10 are regions.

Claims (1)

[Claims] 1. In a semiconductor device in which a substrate bias generation circuit is mounted on a semiconductor substrate, a semiconductor substrate formed in contact with a region where the junction with the semiconductor substrate is in a forward potential state among the regions constituting the substrate bias generation circuit. and the semiconductor substrate is formed around the high concentration region of the same conductivity type as or the region of the substrate bias generation circuit that is in the forward potential state and is connected to a predetermined potential to absorb minority carriers diffused into the semiconductor substrate. 1. A semiconductor device comprising at least one region having an opposite conductivity type.