JPS5949649A - Interruption associated switching circuit for memory bank - Google Patents

Abstract

PURPOSE:To switch memory banks corresponding to respective slave interruption controllers, by using slave identification codes of the slave interruption controllers as bank addresses as they are. CONSTITUTION:A CPU when receiving an interruption signal INT from a master interruption controller 6 outputs an interruption confirmation signal INTA three times. The 1st signal is a slave identification code with which a controller 6 identifies a call instruction for a subroutine and slave interruption controllers 60-67. As the 2nd signal, the low-order eight digit bits of the call address of the subroutine are outputted to a bus 3. As the 3rd signal, the high-order eight bits of the call address of the subroutine are outputted to the bus 3 by the slave identification code, performing interruption processing. At this time, the slave identification code sent out of the controller 6 is latched in a bank address latch 13 as it is, so a bank memory is selected automatically when an interruption occurs to an interruption controller 6i.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an augend memory bank and an augend interrupt controller 0.
The present invention relates to an interrupt-linked switching circuit for a memory bank used in a microcomputer system having:

FIG. 1 is a block diagram showing a microcomputer system having an interrupt controller. In the same figure, (
1) is a CPU, which is connected to peripheral devices via an address bus (2) and a data bus (3). , (4) It is a beam D-tsuku generator, and the CPU fi+ is
The CPU (1) is supplied with a zero clock signal to perform the process. (5) is a system controller inserted in the middle of the data bus (3), which is a bidirectional bus F driver (!:, CP) that assists the bus drive ability of the CPUfl).
[This is a combination of Sdata Sura Sochi (!: chive) that latches the status information output from Jfl+.

(6) is an interrupt controller, and when an interrupt signal is input to interrupt inputs 1RO to IR7 from any of device 06 and device 7, interrupt No. 16 INT is generated and the CPU il)
is input. The CPU (11) outputs an interrupt confirmation signal INTA indicating that the requested interrupt was received as status information, and this is sent to the system controller (5).
)'s status controller (6) receives the interrupt confirmation signal INTA from the system controller i51. This outputs an instruction to call the input processing subroutine onto the data bus (3). (7
) is a decoder which decodes the address data on the address bus (2) and, when it detects a preset address, outputs the child/sive select input JT of the interrupt controller (6) to LL/bevel and interrupts the address data on the address bus (2). This is to select the integrated controller (6). At this time, when the I10 read signal (10R) 75; is output from the system controller (5), the read input (RD
) becomes L level, and the status of interrupt controller (6) is read out to CPIJII). Also, system controller 0-1 (5) to I10 light 1 word (
When the interrupt controller (IOW) is output, the write input (W
Commands from the CPU (11) are written to the controller (6). When using the interrupt controller (6) alone, the terminal SP (slave zero column imp/soto) should be set to H level. It is something to keep.

By the way, in such a conventional example, the interrupt confirmation signal 'kl
Since reception is received with 8 interrupt inputs from RO to IR7, it is 8.
If you need to process more than one interrupt acknowledge signal,
As shown in Fig. 2, the interrupt control roller (6
) and interrupt control for slaves 0-5 (6o) to (6,)
These are connected in cascade so that a maximum of 64 interrupt ammonium signals can be processed. In the system shown in FIG. 2, a masking interrupt controller (6
) as the terminal 5PldH level of the cascade bus C6-
C2 is used as an output ψ, 1M child, and the terminal SP of the slave interrupt controller (6) is set to L level, and the cascade bus Co-C2 is used as an input terminal. In the system shown in FIG. 2, when an interrupt request signal is input to the slave interrupt controller 0-61,
Interrupt input IRi of interrupt controller 0-controller (6) for masking
1 interrupt request signal is transmitted, and the master interrupt control 0-
An interrupt signal INT is sent from the controller (6) to the CPU (IA). CPU (IA) is the CPU in FIG.
This is a CPU that combines a fi+treq generator (4) and a system controller (fl). Interrupt controller for master 0-ra f6]//'iCPU (IA)
When the first interrupt confirmation signal INTτ is received from CP
The U (IA) outputs a call instruction for executing the interrupt processing subroutine to the data bus (3), and also outputs the slave identification codes OOO to Ill via the cascade bus C6-C2 to the interrupt control for slave processing. 0-la (6o)
~(67). Then, the interrupt controller for the slave (6o) corresponding to the sent slave identification code
- (67) outputs a preset call address to the data bus (3) when the remaining two interrupt confirmation signals INTA are sent from the CPU (+). In addition, in this way, an interrupt controller that can be connected in cascade (
6) is Intel's 8259, which has a CPT
J(IA) is the company's 8085. Also this C
The company's 8
080A, 82°8.8°2' till 4 @
War# fc CPU ``t,,/There is a Neil.

By the way, in the conventional example system of FIG. In some cases, the memory space becomes so large that there is no space available for direct access by the CPU (IA).In such cases, there is a method of switching between multiple memory banks with overlapping address spaces. However, each time an interrupt occurs, the CPU (IA) must select the memory bank in which the ``jotaram'' for processing that interrupt is stored, which increases the burden on the CI'1l (IA) and reduces memory usage. There was a problem in that a separate program was required to select the bank and change the bank address.

This was developed in order to solve these problems in the conventional example, and the slave identification code of the slave interrupt controller connected in cascade to the interrupt controller for masking is directly transferred to the bank. It is an object of the present invention to provide an interrupt-linked switching circuit for memory banks that can be used as an address to switch memory banks in correspondence with each slave interrupt controller.

The configuration of the present invention will be described below with reference to illustrated embodiments. Third
The figure shows the overall configuration of a microphone 0 computer system having a memory bank switching circuit (8). In the figure, (IA) is a CPU, and [9] is a ROM. C.P.
The peripheral devices U (IA) are connected via an address bus (2), a data bus (3) and a control bus (lti). (1 is memory bank <Mn) ~(
M2) is a bank address line that cannot be switched to Z].

Figures 1 and 4 show block circuit diagrams of the memory bank switching circuit (8). In the figure, (6) is a masked interrupt controller, and the terminal SP is set to H level and is used as a power terminal for the cascade buses C6 to Cz)j. Also (6o) ~ (6y) iJ: Interruption for slaying]
The input terminal 7 is the cascade bus C8-c2 with the terminal 0-'s set to 0-0 and the terminal 0-'s P-keL.

Interrupt request signals from devices 0 to 63 are input to the interrupt inputs IRO to IR7 of the controllers (6o) to (67). Interrupt signal from (67)
NT is connected to each interrupt input IRO^IR7 of the interrupt controller 0-6 for masking. Therefore, when an interrupt request signal is input to the interrupt controller (61) for slaying, the interrupt controller (61) for masking
6) The interrupt signal INT from the slave interrupt controller (61) is input to the interrupt input I<i. This causes an interrupt for the mask to be generated from the t-roller f6).
An interrupt INT is sent via the control bus l[]). This interrupt signal IN
It is also input to the data selector (12), and when an interrupt is activated, the contents of the e(-) lead bus C1l''C2 are input to the 'bank address Utsuchi(+ +J), and the normal The contents of the data bus (3) are input to the bank address latch (131) at time r (at time r).In other words, at normal times, the contents of the data bus (3)
When switching the bank address of (M,), the bank address is transferred from the data bus (3) to the data selector (1).
2) Enter the basiquad and input the latch θ3s K through the CPU (IA). The bank address 51υch (
When the bank address is input to the bank address latch (1: (i)), the bank address is latched to the bank address latch (1: (i). Note that in this embodiment, there are only 8 memory banks (81°) to (817), so the bank address of 8 hints (of 1, only the lower 3 is what is used.

When the CPU (IA) receives the interrupt signal INT from the mask interrupt controller (6), it loads the call instruction and call address of the interrupt processing routine. Interrupt confirmation a, e signal I NT Ai output 3 times. 1st interrupt confirmation signal INTA = ', When the reception is settled, the mask interrupt controller (6) Tsumugi data bus (
3) Output the subroutine call instruction above. In the case of Intel's 8080 and 8085, the ]-le command in this subroutine is $CD in hexadecimal, and therefore the]-code is output to 1 of the 8 characters on the data bus f311c 111o o 1101-1. It is. In addition, this old masked J's interrupt controller 0-ra (6) is the interrupt controller for the slave (6o) to (6,) that was asked to interrupt the Nokoskate bus C3-c2. This outputs the S/L/TJ identification code for identifying the SL/TJ. Then, the second interrupt confirmation number h INTA is CPU
When output from (IA), an interrupt for the slave selected by the slave identification code is outputted from 0-ra (6o) to (6o).
From t+y), the lower 8 hits of the subroutine which is the override of the command are output to the data bus (3)K, and the third interrupt is also confirmed? a (ittJ NT
When A is output from CP tJ (IA, ), the interrupt controllers (6o) to (67) for the slave selected by the slave identification code t1 to Suzurouchi's]-
The top 8 results of the top 8 results are output to the data bus (3). As a result, C)'U(IA) executes the interrupt processing subroutine corresponding to each interrupt confirmation signal.

At this time, on the bank address line f11), there is a cascade path C from the mask interrupt controller (6).
Since the slave identification code sent to o, -C, is latched and output as is by bank address 03J, interrupt ml? When an interrupt confirmation signal is input to the controller (61) and an interrupt occurs, the bank meter (λfi) is automatically selected.

The present invention is configured as described above, and includes a plurality of memory banks redundantly connected to the same address space accessed by the CPU; A masking interrupt that inputs an interrupt signal and outputs a subroutine call instruction on the CPU's data bus when receiving an interrupt confirmation signal from the CPU] and multiple masking interrupt controllers. When an interrupt occurs in the interrupt input, interrupt 1g to the master cutting controller □-
When the slave identification code output from the mask interrupt controller 0-controller matches its own code, the interrupt processing subroutine corresponding to each interrupt input is executed following the above call instruction. An interrupt controller for multiple slaves that outputs the reference point on the data bus of the CPU, and a memory bank that latches the slave identification code when receiving an interrupt confirmation signal from the CPU. Since the interrupt controller for masking has a bank address line that is output to the bank address line of the memory bank, the slave identification code used to select the interrupt controller for the slave is directly transferred to the bank of the memory bank. It can be used as an address, and therefore, each time an interrupt occurs, there is no need to use the CPUK to select a memory where the program to handle the interrupt is stored, and this reduces the burden on the CPU. This has the advantage that it is not necessary to create an 11L column for switching the bank address of the memory bank in response to an interrupt request signal.
P [When receiving an interrupt confirmation signal from J, I changed the jump identification code to the bank address, so even if an interrupt occurs, the CPU can check the interrupt with the interrupt disabled. If no signal is sent, there is an advantage that the bank address of the memory bank can be prevented from being changed inadvertently.

[Brief explanation of the drawing]

Figure 1 is a 5099 diagram of a conventional example, and Figure 2 is a '5099 diagram of another conventional example.
:5o・ν diagram, Figure 18 is 5099 of one embodiment of the present invention.
Figure 4 is a schematic diagram of the main parts of the same as above. flJ (IA) tj: CPU, (3) Hard data path, (61 (6o) - (6y) #'1 interrupt control 0
-La, (1 is bank address line (1,1 is bank address latch, IRO~IR7#'i interrupt input, (8ln
) ” (My) If'i memory bank, co-c2
is a cascade bus. 31 Patent Attorneys Choshichi Ishi

Claims (1)

[Claims] (1) 'I' in the same address space accessed by the CPU
IL multiple connected memory banks and CP
Connected to the interrupt input of tJ, inputs an interrupt signal to the CPU when an interrupt occurs, and inputs an interrupt signal to the CPU when an interrupt confirmation signal is received from the CPU.
A masking interrupt controller 0- that outputs the call instruction of the Ktj brutine on the data bus of the PU is connected to the interrupt inputs of the masking interrupt controller 0-, and a plurality of When an interrupt occurs, an interrupt signal is input to the masking interrupt controller, and the slave identification code output from the masking interrupt controller matches its own code. Sometimes, an interrupt controller for multiple slaves outputs a call band of a subroutine for interrupt processing corresponding to each interrupt input onto the data bus of the CPU following the above call instruction, and an interrupt controller from the CPU. An interrupt-linked switching circuit for a memory bank, comprising a bank address latch that latches the slave identification code and outputs it to a bank address line of the memory bank when receiving a confirmation signal.