JPS594367A - Signal detector - Google Patents

Abstract

PURPOSE:To vary a tone frequency to be detected, by performing addition or subtraction at a counter in response to an output of memory and detecting that the counter value attains a prescribed value. CONSTITUTION:A tone input is waveform-shaped into a pulse P1 at a waveform shaping circuit 1. A detecting circuit 2 detects the leading and trailing of the pulse P1 and a pulse P2 is outputted. A counter 4 counts the period of the pulse P2. This count value is transferred to a memory 5. A counter 6 makes up or down-count according to the command of the memory 5. A memory 7 gives an output when the value (m) of the counter 6 is a prescribed value or over. The frequency of the detected tone is changed by changing the command of the memory 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (a. Field) The present invention is a signal detection method that can detect signals of a specific frequency such as a carrier with a highly versatile configuration in a device such as a modem that constantly monitors received signals connected to a line. Regarding equipment.

(b. Renal system of technology) In general, in a communication system that connects a modem to a line, at the beginning of communication, a specific carrier signal (called a tone) is sent out and communication is initiated from the sending side to the receiving side. A notice is being sent to the effect that

(c. Prior Art) Conventionally, in order to detect such a tone 7, a filter for extracting the relevant frequency is used, and the filter is configured to detect that a tone is detected for a certain period of time. .

However, with such a conventional configuration, it is necessary to design a filter individually depending on the frequency of the tone used, and the detection device has the disadvantage that it is not versatile.

(d. Object of the Invention) An object of the present invention is to provide a highly versatile signal detection device in order to eliminate the conventional drawbacks.

(e. Key Points of the Invention) In order to achieve the above object, the present invention provides a memory that stores addition/subtraction instruction data corresponding to the period of the signal, and performs addition/subtraction according to the output of the pain pattern mesori. , tde is designed to detect signal reception by counting the number of consecutive days with the same cycle as 1.

(f. Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart thereof.

In the figure, 1 is a waveform shaping circuit, 2 is a force detection circuit, 3 is a clock oscillator, 4 is a counter, 5 is a frequency detection memory,
6 is an up/down counter, and 7 is a memory for detection output.

Further, the waveform shaping circuit 1 shapes the tone human power 1 into a square wave P1, and the rising edge detection circuit 2ii shapes the square wave P.

The rising edge of P! is detected in synchronization with the output of clock oscillation B3, and the pulse signal P! The counter 4 measures each period from the falling edge to the falling edge of the pulse P2 by counting three times the output of the clock oscillator, and outputs the count value n. The count value is reset at the rise of the pulse P. The frequency detection memory 5 is accessed at the falling edge of the pulse PI by setting the count value n of the counter 4 to 7 addresses, and the storage address of the count value corresponding to the cycle to be detected contains data U instructing up-counting, that is, addition. However, data D instructing down-counting, that is, subtraction, is stored at the storage address of the count value corresponding to the period that should not be detected.

Therefore, if it is a signal that should be detected according to the count value of the counter 4 at the time of access (if it is the M number, the addition instruction data U should not be detected, then the subtraction data D is output. According to the instructions from the memory 5, the corresponding operation, that is, up-counting or down-counting, is performed and the counted value m is output.
The count value of is used as an address, and a count value d indicating whether or not a tone is input is stored in the corresponding storage address.

In Fig. 2, the internal tone TON input manually is the tone to be detected, and in the tone input to explain the operation of MiJ1, the pulse P1 is input to the waveform shaping circuit.
The waveform is shaped into The rising edge of the pulse P output from the waveform shaping circuit 1 is detected by the rising edge detection circuit 2, and the pulse P is output.

The counter 2 measures the period of the pulse horse, and this count value 3 is transferred to the shift memory 5 by the next pulse P snow, and
will be reset. In this example, the value of n is 5 in memory 5.
Busy instruction data for each corresponding address is entered so that the count is counted up only when the value is 1, and the count is down counted when the value is other than 1.

Therefore, signal U (up-count instruction data) is read during period TOH, and signal D (down-count instruction data) is read during other periods. Counter 6 is pulse P
, therefore, the value of the absolute value %IN is counted up or down according to the instructions in the memory 5. Therefore, the tone period TON to be calculated is the up count instruction data U.
are continuous, so when the tone period TON begins, the count value increases rapidly and reaches the highest value K of the counter 6 (value %5# in this example).

The memory 7 stores data such that when the value m of the counter 6 is equal to or greater than -3, a signal is output as a level note IN, and when the value is less than that, a signal is output as a level whisper OI.

Therefore, after entering the tone period TOH, the counter 6 shows the value %.
3), that is, the tone can be detected and output after a predetermined detection period, and the tone is further removed from the tone period TON, and the period To is until the counter 6 becomes less than or equal to the value 13I, and the tone is delayed and removed from the tone period TON. can detect that something has happened.

(g-Effect of the Invention) As described above, according to the present invention, data indicating that up-running is in the memory 5 corresponding to the cycle to be detected, that is, the count value of the counter 4, is stored as the down-count value. According to the embodiment, the data stored in the memory 7 can be rewritten, for example, the counter If the count value of 6 is more than -4〃, level ^1〃, if the value is less than 3N, level ki O
If you change the data so as to output 〃, the detection period Ti + T
It also has the effect of being able to adjust o.

[Brief explanation of the drawing]

1 and 2 are a block diagram and a time chart of an embodiment of the present invention. In the figures, 2 is a rising edge detection circuit, 4 and 6 are counters, and 5.7 is a memory.

Claims (1)

[Claims] means for creating a signal synchronized with the cycle of an input signal; a means for timing the cycle; the clock value is used as an address; when the cycle is the cycle of the signal to be detected, an addition (or subtraction) output is generated; A ml memory that outputs a subtraction (or addition) output when the period is not the desired signal period, a counter that adds or subtracts a predetermined value according to the output of the meso, and detects that the counter has reached a predetermined value. and means for notifying that a signal to be detected has been input.