JPS593542A - Data transferring system - Google Patents

Data transferring system

Info

Publication number
JPS593542A
JPS593542A JP57113397A JP11339782A JPS593542A JP S593542 A JPS593542 A JP S593542A JP 57113397 A JP57113397 A JP 57113397A JP 11339782 A JP11339782 A JP 11339782A JP S593542 A JPS593542 A JP S593542A
Authority
JP
Japan
Prior art keywords
dummy
data
register
sent
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57113397A
Other languages
Japanese (ja)
Inventor
Koji Torii
鳥井 浩治
Hisashi Tanaka
尚志 田中
Yuichi Ito
祐一 伊藤
Mikitaka Murase
村瀬 幹卓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57113397A priority Critical patent/JPS593542A/en
Publication of JPS593542A publication Critical patent/JPS593542A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To raise remarkably the operation efficiency of a system, by transmitting a dummy signal of quantity corresponding to the processing capacity of plural input/output devices. CONSTITUTION:By an operation control of a microprocessing device MPU, first of all, the processing capacity is inquires to each device, and its response is stored in a register R-A. Subsequently, the device MPU sets an instruction to be sent to a high speed input/output device I/O1, to a data setting register R-B, and sets a corresponding dummy quantity ''1'' to a counter CNT. In this case, a countact of a switching circuit SW is set to the side (a) and the instruction is sent to a transmission line TL. Subsequently, the contact is set to (b), and a dummy signal stored in a high speed I/O device dummy register R/D is sent out to a transmission line TL. Also, in case when the device I/O is for medium and low speed use, a counting value of the corresponding counter CNT is set from the register R-A, so that a data is sent, following a dummy quantity of ''5'', for instance, of 5 times of that in case of a high speed ''1''.

Description

【発明の詳細な説明】 (1)  発明の技術分野 本発明は処理能力の異なる複数の入出力装置について本
来の処理能力を十分に発揮できるように制御するデータ
転送方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a data transfer system that controls a plurality of input/output devices with different processing capabilities so that they can fully utilize their original processing capabilities.

(2)従来技術と問題点 比較的高速でデータ転送を行なう場合データの先頭にコ
マンドとダミーを付加し第1図のように行なっている。
(2) Prior Art and Problems When data is transferred at a relatively high speed, a command and a dummy are added to the beginning of the data as shown in FIG.

複数の入出力装置l101 e l102*がコマンド
CMDを受取ってからデータDTを受取るための準備K
idする時間(立上り時間)は、入出力装置毎に異なる
ため(処理能力の異なる一つの例)、それを吸収するよ
うに例えば最も低速処理のできる入出力装置に対応する
値のダミー量DM1.DM2.・・・を付加して他の高
速装置宛・中速装置宛にも送出する。そのため折角高速
処理のできる入出力装置を使用してもダミ一部の部分に
ついては転送能力・処理能力が落ちる原因となる。
Preparation K for multiple input/output devices l101 e l102* to receive data DT after receiving command CMD
Since the time for id (rise time) differs for each input/output device (an example of a different processing capacity), a dummy amount DM1. DM2. ... is added and sent to other high-speed devices and medium-speed devices as well. Therefore, even if an input/output device capable of high-speed processing is used, the transfer ability and processing ability will deteriorate in some areas.

OTLは制御装置である。OTL is a control device.

(3)発明の目的 本発明の目的は前述の欠点を改善し入出力装置毎にダミ
ーの量を異ならせてデータ転送を行なうことにより十分
に処理能力を発揮させたデータ転送方式を提供すること
にある。
(3) Purpose of the Invention The purpose of the present invention is to improve the above-mentioned drawbacks and to provide a data transfer method that fully utilizes processing ability by transferring data with different amounts of dummy for each input/output device. It is in.

(4)発明の構成 前述の目的を達成するための本発明の構成は、データフ
ォーマットの先頭にコマンドを設け、所定データとの間
にダミー情報を挿入し、処理能力の異なる複数の入出力
装置へのデータ転送を制御する制御装置を有する情報処
理システムのデータ転送方式において、転送フォーマッ
トがコマンド・ダミー・データの3種類で形成される場
合、ダミーの量として入出力装置の処理能力に対応する
童を設定することである。
(4) Structure of the Invention The structure of the present invention to achieve the above-mentioned object is to provide a command at the beginning of a data format, insert dummy information between predetermined data, and connect multiple input/output devices with different processing capabilities. In a data transfer method for an information processing system that has a control device that controls data transfer to a computer, if the transfer format is formed of three types: command, dummy, and data, the amount of dummy corresponds to the processing capacity of the input/output device. It is to set children.

(5)発明の実施例 第2図は本発明の一実施例として第1図に示す制御部の
構成を詳細に示す図である。システム内入出力装置の処
理能力の異なっていることが判っているとき、マイクロ
プロセッサMPUの動作制御により最初に各装置に対し
処理能力を間合せ、その応答を装置毎の状態を記憶する
レジスタR−ム に格納する。マイクロプロセッサMP
Uはデータセット用レジスタR−B  K対し高速入出
力装置l101に送るコマンドをセットし、次にカウン
タONT K高速入出力装置 rlo I K対応する
ダミー蓋として「1」を七ッ卜する。切替回@SWの接
点をa側にして、前記コマンドを伝送線に送る。
(5) Embodiment of the Invention FIG. 2 is a diagram showing in detail the configuration of the control section shown in FIG. 1 as an embodiment of the invention. When it is known that the processing capabilities of input/output devices in the system are different, the microprocessor MPU first adjusts the processing capabilities of each device by controlling the operation, and the response is stored in a register R that stores the status of each device. − Store in . microprocessor mp
U sets a command to be sent to the high-speed input/output device l101 in the data set register R-BK, and then sets "1" to the counter ONT K as a corresponding dummy lid. Set the contact of the switching circuit @SW to the a side and send the above command to the transmission line.

次に接点なりとし高速入出力装置ダミー用レジスタR−
D  K予め格納さhでいたダミー信号を伝送線TLに
送り出す。カウンタGNTKより接点すはダミー数「1
」のみで接点aに切替る。レジスタR−B はコマンド
送出の後マイクロプロセッサMPUがメモリMEMを読
出して所定のデータを入れるから、データDT は順次
接点aを介して伝送される。
Next, the high-speed input/output device dummy register R-
DK sends out the dummy signal stored in advance to the transmission line TL. From the counter GNTK, the contact point is the dummy number “1”.
” to switch to contact a. After sending the command, the microprocessor MPU reads out the memory MEM and stores predetermined data in the register R-B, so that the data DT is sequentially transmitted via the contact a.

入出力装置工10が中速・低連用の場合はそhに対応す
るカウンタCNTの計数値をレジスタR−A からセッ
トする。例えば計数値を「5」とセットしたとき前述の
説明時間の5倍の時間だけ切替回路SWの接点をb側に
する。
When the input/output device 10 is for medium speed/low continuous use, the corresponding count value of the counter CNT is set from the register RA. For example, when the count value is set to "5", the contact of the switching circuit SW is set to the b side for a time that is five times the time described above.

そのためコマンドに続くダミー量は「5」だけ続いて伝
送され、次にデータが伝送される。
Therefore, the dummy amount "5" following the command is transmitted successively, and then data is transmitted.

(6)発明の効果 このようにして本発明によると複数の入出力装置につい
てその処理能力に応じた量のダミー信号が伝送されるた
め、高速処理のできる装置であればデータもそのように
伝送さね、また低速処理の装置であればデータがゆっ(
り到来するので、システムの動作能率が極め萌 て直上できる。
(6) Effects of the Invention In this way, according to the present invention, dummy signals are transmitted in an amount corresponding to the processing capacity of multiple input/output devices, so if the device is capable of high-speed processing, data can also be transmitted in this manner. Also, if it is a low-speed processing device, the data will be processed slowly (
As a result, the operating efficiency of the system can be maximized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のデータ転送方式の説明図、第2図は本発
明の一実施例の構成を示す図である。 OTL・・・制御装置      Ilo 1 、 I
lo 2・・・入出力装置MIEM・・・メモIJ  
      MPU・・・マイクロコンピユー夛R−A
、R−B、R−D・・・レジスタCNT・・・カウンタ
    SW・・・切替回路特許出願人  富士通株式
会社 代 理 人 弁理土鈴木栄祐 第1図
FIG. 1 is an explanatory diagram of a conventional data transfer system, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. OTL...control device Ilo 1, I
lo 2...Input/output device MIEM...Memo IJ
MPU...Microcomputer R-A
, R-B, R-D...Register CNT...Counter SW...Switching circuit Patent applicant Fujitsu Ltd. Agent Eisuke Tsuchi Suzuki Figure 1

Claims (1)

【特許請求の範囲】[Claims] データフォーマットの先頭にコマンドを設け、所定デー
タとの間にダミー情報を挿入し、処理能力の異なる複数
の入出力装置へのデータ転送を制御する制御装置を有す
る情報処理システムのデータ転送方式において、転送フ
ォーマットがコマンド・ダミー・データの5種類で形成
される場合、ダミーの量として入出力装置の処理能力に
対応する量を設定することを特徴とするデータ転送方式
In a data transfer method for an information processing system that includes a control device that provides a command at the beginning of a data format, inserts dummy information between it and predetermined data, and controls data transfer to multiple input/output devices with different processing capabilities, A data transfer method characterized in that when a transfer format is formed of five types of commands, dummy data, and data, an amount corresponding to the processing capacity of an input/output device is set as the amount of dummy.
JP57113397A 1982-06-29 1982-06-29 Data transferring system Pending JPS593542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57113397A JPS593542A (en) 1982-06-29 1982-06-29 Data transferring system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57113397A JPS593542A (en) 1982-06-29 1982-06-29 Data transferring system

Publications (1)

Publication Number Publication Date
JPS593542A true JPS593542A (en) 1984-01-10

Family

ID=14611260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57113397A Pending JPS593542A (en) 1982-06-29 1982-06-29 Data transferring system

Country Status (1)

Country Link
JP (1) JPS593542A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10938279B2 (en) 2018-01-05 2021-03-02 Rolls-Royce Plc Electrical machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10938279B2 (en) 2018-01-05 2021-03-02 Rolls-Royce Plc Electrical machine

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