JPS5932143A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5932143A
JPS5932143A JP57142912A JP14291282A JPS5932143A JP S5932143 A JPS5932143 A JP S5932143A JP 57142912 A JP57142912 A JP 57142912A JP 14291282 A JP14291282 A JP 14291282A JP S5932143 A JPS5932143 A JP S5932143A
Authority
JP
Japan
Prior art keywords
pad
layer
film
strength
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57142912A
Other languages
Japanese (ja)
Inventor
Hirofumi Motohara
本原　裕文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57142912A priority Critical patent/JPS5932143A/en
Publication of JPS5932143A publication Critical patent/JPS5932143A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Abstract

PURPOSE:To improve the bondability and strength of a junction pad by forming a metal layer of the same type as the pad under the pad or further forming a layer which has good bondability with an oxidized film of Ti or Cr or the like under the pad. CONSTITUTION:A pad which is superposed with an aluminum layer 16 is formed on a Ti film 15 on an SiO2 film 22 of an Si substrate 21, and an aluminum layer 17 is deposited thereon. A resist mask 18 is covered, the pad 13 and the layer 17 except the wirings are etched, and a PSG film 19 is covered on the part except the pad. According to this configuration, the margin of the strength can be increased for the reproduction of the junction due to the interposition of the Ti or Cr layer, and the strength required for the pad and the strength due to the load of the metal layer formed under the pad can be increased, and the thickness of the metal film for the wirings can be considerably reduced.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はポンディングパッドの密着力及び強度を向」
二さｂるよう（二した半導体装置の製造方法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention improves the adhesion and strength of a bonding pad.
This invention relates to a method for manufacturing a semiconductor device.

〔発明の技術的背景〕[Technical background of the invention]

従来のポンディングパッドの構造について第１図を用い
て説明する。同図（Ｎはポンディングパッドの平面図、
同図（Ｂ）はその断面図である。The structure of a conventional bonding pad will be explained with reference to FIG. The same figure (N is the plan view of the pounding pad,
The same figure (B) is the sectional view.

同図（Ａｌにおいて、ＰＳＧＩ峠１１の開「］部にポン
ディングパッド１２が形成されている。このポンディン
グパッド１２は金属配線として用いられるＡ　Ｉ　Ｉｔ
ｌｍ　Ｊ　、ｑと一体形成されている。次（二、同図ｔ
ｎ＋において、２１は半導体基板、２２け上記半導体基
板上Ｃ形成された酸化膜（Ｓｉ０２膜）である。そして
、上記酸化膜２２上にはＡＩ！層１３が蒸ｖ！＃サレテ
オリ、」−記Ｐ８０ＩｐＨＯ）開口部に位置するＡｌ１
１４ｙｓ＋ニボンデイングパツド１２が形成されている
。In the same figure (in Al, a bonding pad 12 is formed in the open part of the PSGI pass 11. This bonding pad 12 is used as a metal wiring.
It is integrally formed with lm J and q. Next (2, same figure t
In n+, 21 is a semiconductor substrate, and 22 is an oxide film (Si02 film) formed on the semiconductor substrate. Then, on the oxide film 22, there is an AI! Layer 13 is steamed! #Sareteori,” - P80IpHO) Al1 located at the opening
14ys+nibonding pad 12 is formed.

〔背Ｊ＋技術の間Ｍ身点〕[Back J + technique M body point]

上記したＩＡＣ１図ｔｅｌに示した断面を有するボンデ
ィングパラＦ１２（ニボンデイングマシンによりワイヤ
ボンディングを行った場合ボンディングの条件（温糺、
荷Ｎ等）の変動に対してマージンが少ないという欠点が
あった。例えば、ポンディングパッド１２（一対してボ
ンディングをやり直すとき（二、ポンディングパッド１
２のに４ｆｆ４１．９が酸化膜２２から剥離してしまう
という欠点があった。Bonding Parameter F12 having the cross section shown in the above-mentioned IAC1 figure (tel)
There was a drawback that there was little margin for fluctuations in load N, etc.). For example, bonding pad 12 (when re-bonding a pair (2, bonding pad 1
No. 2 had the disadvantage that 4ff41.9 peeled off from the oxide film 22.

〔発明の目的〕[Purpose of the invention]

この発明は上記の点（−龜みてなされたもので、その目
的はポンディングパッドの密着力及び強度を向上させる
ようにした半導体装置の製造方法を提供することにある
。The present invention has been made in view of the above points, and its object is to provide a method for manufacturing a semiconductor device that improves the adhesion and strength of a bonding pad.

〔発明の棚・掛〕[Shelf/hanging of invention]

ポンディングパッドを形成する３２合にポンディングパ
ッドのＦにパッドと同じあるいはそれより大きい金属層
を形成している。この金属層はパッドと同じ金属層を一
層設けるかパッドと同じ金１に層のドにさらにＴｒある
いはＯｒ等のＦ地の酸化膜と密着性の良い金属層を形成
している。At 32 points forming the bonding pad, a metal layer that is the same as or larger than the pad is formed on F of the bonding pad. For this metal layer, the same metal layer as the pad is provided, or a metal layer having good adhesion to the F-based oxide film, such as Tr or Or, is formed on the same gold layer as the pad.

〔発明の実施例〕 以丁、図面を参照してこの発明の一寅施例を説明する。[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

同実施例においてはボンデイングバツドドに形成する金
Ｍ胸をリフトオフ法で形成する場合について述べる。ま
ず、第２図（Ａ）において、２１は半嗜体＆板、２２は
一ヒ記半導体基板１１上（二形成された８１０．層であ
る。そして、上記Ｆ３ＩＯ，１ｌｊ２２上のポンディソ
ゲバッド部１３以外（Ｚレジスト１４を形成させる。次
に、上記８１０．ＩＱ２．２と密着力の強イ’ｒ　Ｉ　
ＩＦ１１５を例えば５００〜８００／ｆ　　蒸着し、そ
の上（二、工程中（二おけるＴｉ１ｌの酸化を防止する
意味で、ｋｌ＠１６を例えば１μ程度蒸着する。次＋二
、同図（Ｂｌに示すように、−に記しジスト１４を剥離
することにより、同時（二、レジスト１４上に蒸着され
ていた’Ｉ’Ｉ層ｘｓ７ＪびＡｌｒｆ４１ｅを除去し、
ボンディングパット部１３におけるＴ１層１５及びＡＪ
Ｉ尚１６はそのまま残留する。次に、同図（０１に示す
よう（二金属配線となるＡ　Ｉ　ＩＷｎ　？　ｙを蒸冷
する。そして同ＩＩ　（ｔ＋）−二示すようＣニボンデ
イングパッド部１３及び金属配線以外にレジスト１８を
形成する。次に、同図（Ｐり　＋−示すようにポンディ
ングパッド部１３及び金属配線以外のＡＪｌｉ７７を除
去する。そして、同図（鱒に示すようにボッディングパ
ッド部１３以外（二保腹用のＰＳＧＩＦＩＪ９を形成す
る。In this embodiment, a case will be described in which a gold M breast formed on a bonding butt is formed by a lift-off method. First, in FIG. 2(A), 21 is a half board & board, 22 is a layer 810 formed on the semiconductor substrate 11 mentioned above. Other than the part 13 (form the Z resist 14. Next, the above-mentioned 810.IQ2.2 and the strong adhesive resist I'r I
IF115 is deposited at a rate of, for example, 500 to 800/f, and then kl@16 is deposited, for example, at a rate of about 1 μm, in order to prevent the oxidation of Ti1l during the process (2). As shown in -, by peeling off the resist 14, simultaneously (2) remove the 'I'I layer xs7J and Alrf41e deposited on the resist 14,
T1 layer 15 and AJ in bonding pad portion 13
Note that 16 remains as is. Next, as shown in FIG. 1 (01), the A I IWn? Next, remove the AJli 77 other than the bonding pad part 13 and the metal wiring as shown in the same figure (Pri +-). Form PSGIFIJ9 for the abdomen.

なお、上記実施例においてはポンディングパッド部１３
の下層喀二Ｓｉｎ、層Ｊ２と密着性の強いＴＩ％７５を
形成したが、Ｏｒ層でも良い。In addition, in the above embodiment, the bonding pad portion 13
Although a TI% 75 layer with strong adhesion to the lower layer J2 was formed, an Or layer may also be used.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明Ｃ二よれば、ポンディング
パッド部の最ＦＭにｆ地のＳｉ０１層と密着性の強い金
属−胸を形成したので、ポンディングのやり直しなどに
対する強度マージン上昇する。さらＣ二、ポンディング
パッドに要求される強度をポンディングパッド部ドＣ二
形成される金属層に負担させることにより強度を増強す
ることができる一方、金属配線形成用の金属膜をかなり
薄くすることが可能となり、微細なパターンの形成も容
易となる。As described in detail above, according to invention C2, a metal breast with strong adhesion to the Si01 layer of the f base is formed at the most FM of the bonding pad portion, so that the strength margin for redoing bonding etc. is increased. Furthermore, the strength required for the bonding pad can be increased by having the metal layer formed at the bonding pad part bear the strength, while the metal film for forming the metal wiring can be made considerably thinner. This makes it possible to easily form fine patterns.

【図面の簡単な説明】[Brief explanation of drawings]

第１図囚は従来のポンディングパッドを示す平面図、同
図（Ｅｌはその断面図、第２図ｔＡｌ　−ｔＦｌはこの
発明の一実施例における半導体装置の製造方法を示す図
である。 ｘ５−−−ＴＮ＠、１６　、　Ｊ　７・・−ＡＪｊＮ、
１４゜１８・・・レジスト。 出願人代理人　４ｒ理士　鈴　江　武　彦第１図 第２図 ３FIG. 1 is a plan view of a conventional bonding pad, El is a cross-sectional view thereof, and FIG. ---TN@, 16, J7...-AJjN,
14°18...Resist. Applicant's agent 4r Physician Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）　　半導体装置のポンディングパッド形成領域に
酸化膜に対して密着力の強い第１の金ｐ４層を形成する
工程と、上記第１の金属層上に第２の金属層を形成する
工程と、上記第２の金属層上及び他の配線領域（−上記
第２の金属層と同種の金属層を形成する工程とを具備し
たことを特徴とする半導体装置の製造方法。(1) A step of forming a first gold p4 layer having strong adhesion to an oxide film in a bonding pad formation region of a semiconductor device, and a step of forming a second metal layer on the first metal layer. and a step of forming a metal layer of the same type as the second metal layer on the second metal layer and other wiring regions. （２）　　上記第１の金ＩＰ７４層はＴ１あるいはＯｒ
であることを特徴とする特許請求の範囲第１　Ｊ（ｉ記
載の半導体装置の製造方法。(2) The first gold IP74 layer is T1 or Or
The method for manufacturing a semiconductor device according to claim 1J(i), characterized in that:
JP57142912A 1982-08-18 1982-08-18 Manufacture of semiconductor device Pending JPS5932143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57142912A JPS5932143A (en) 1982-08-18 1982-08-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57142912A JPS5932143A (en) 1982-08-18 1982-08-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5932143A true JPS5932143A (en) 1984-02-21

Family

ID=15326505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57142912A Pending JPS5932143A (en) 1982-08-18 1982-08-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5932143A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219934A (en) * 1986-03-22 1987-09-28 Nec Kansai Ltd Semiconductor device
US6723628B2 (en) 2000-03-27 2004-04-20 Seiko Epson Corporation Method for forming bonding pad structures in semiconductor devices
US6812123B2 (en) 2000-03-27 2004-11-02 Seiko Epson Corporation Semiconductor devices and methods for manufacturing the same
JP2014123611A (en) * 2012-12-20 2014-07-03 Denso Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219934A (en) * 1986-03-22 1987-09-28 Nec Kansai Ltd Semiconductor device
US6723628B2 (en) 2000-03-27 2004-04-20 Seiko Epson Corporation Method for forming bonding pad structures in semiconductor devices
US6812123B2 (en) 2000-03-27 2004-11-02 Seiko Epson Corporation Semiconductor devices and methods for manufacturing the same
JP2014123611A (en) * 2012-12-20 2014-07-03 Denso Corp Semiconductor device

Similar Documents

Publication Publication Date Title
JPH0590350A (en) Semiconductor device
JPH07506702A (en) Ridge-free bonding process with multilayer metallization
JP2633586B2 (en) Semiconductor device having bump structure
JPS59202636A (en) Formation of fine pattern
JPS5932143A (en) Manufacture of semiconductor device
JPS61172362A (en) Bonding electrode structure
JPH0245967A (en) Manufacture of lead frame for semiconductor device
JP3765565B2 (en) Electronic circuit board
JP3816348B2 (en) Metal bonding coating
JP2691103B2 (en) Lead frame manufacturing method
JPS63177543A (en) Lead frame for semiconductor device
JPS6247139A (en) Forming method for transfer bump substrate
JPH02187045A (en) Formation of facedown bonding pad
JPS61172361A (en) Manufacture of tape carrier
JPS63161646A (en) Manufacture of semiconductor device
JPS5795626A (en) Manufacture of semiconductor device
JPH0737147B2 (en) Thermal head and manufacturing method thereof
JPH0198238A (en) Method of mounting semiconductor device
JPS60152046A (en) Semiconductor device
JPH0287538A (en) Tape carrier module
JPS6270594A (en) Selective plating method
JPH07221102A (en) Structure of bump electrode of semiconductor device and formation of bump electrode
JPS63252445A (en) Manufacture of semiconductor device
JPH03132036A (en) Manufacture of semiconductor device
JPH01241116A (en) Alignment-mark