JPS5926886B2 - Error detection method in mobile body position detection device - Google Patents
Error detection method in mobile body position detection deviceInfo
- Publication number
- JPS5926886B2 JPS5926886B2 JP3352176A JP3352176A JPS5926886B2 JP S5926886 B2 JPS5926886 B2 JP S5926886B2 JP 3352176 A JP3352176 A JP 3352176A JP 3352176 A JP3352176 A JP 3352176A JP S5926886 B2 JPS5926886 B2 JP S5926886B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- position detection
- error
- absolute address
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Length Measuring Devices With Unspecified Measuring Means (AREA)
Description
【発明の詳細な説明】
この発明は、走行うレーンや列車等の位置を検出する装
置、特に絶対位置を番地として検出する絶対位置検出装
置において、検出した番地が正しいか否かを判定して検
出する移動体位置検出装置における誤り検出方法に関す
るものである。[Detailed Description of the Invention] The present invention is a device for detecting the position of a running lane or a train, particularly an absolute position detecting device that detects an absolute position as a street address, by determining whether or not the detected street address is correct. The present invention relates to an error detection method in a mobile body position detection device.
通常、絶対位置検出装置において、絶対位置は2進符号
で表わされる番地であり、従来、その符号において、゛
1’’あるいばo’’の数を奇数もしくは偶数にするよ
うに余分のビットを付加し、この2進符号の誤りの有無
を検出していた。このためその符号の偶数個ビットに誤
りを生じた場合は誤りとして検出できない。また、位置
検出は長い距離にわたつて行われるために、余分のビッ
ト、すなわちパリテイビットを付加することは経済的で
はなかつた。この発明は上述の欠点を除くために、パリ
テイビットを付加しないで位置検出の誤りを判定できる
ようにしたものである。Usually, in an absolute position detection device, the absolute position is an address represented by a binary code, and conventionally, in that code, extra bits are added to make the number of ``1'' or o'' into an odd or even number. was added to detect the presence or absence of errors in this binary code. Therefore, if an error occurs in an even number of bits of the code, it cannot be detected as an error. Furthermore, since position detection is performed over a long distance, it is not economical to add extra bits, that is, parity bits. In order to eliminate the above-mentioned drawbacks, this invention makes it possible to determine errors in position detection without adding parity bits.
その原理を説明すると、位置検出において移動体の移動
に伴う番地の変化を予測することは容易であるから、現
在の番地が以前に得られた番地と比較して一定の相関の
もとにあるかどうかを判定すれば、その位置検出が正し
いかどうか判別できるわけである。相関としては、右側
番地、左側番地および同一番地(停止)があり、これら
以外の番地となつた場合には誤りとなるわけである。以
下図面によつてこの発明を説明する。図面はこの発明の
一実施例を示す構成略図である。To explain the principle, it is easy to predict changes in address due to the movement of a mobile object in position detection, so there is a certain correlation between the current address and the previously obtained address. By determining whether or not the position detection is correct, it is possible to determine whether or not the position detection is correct. Correlations include the right address, the left address, and the same address (stop), and if the address is any other than these, it will be an error. The present invention will be explained below with reference to the drawings. The drawing is a schematic diagram showing an embodiment of the present invention.
この図において、1は移動通路に沿つて設置される絶対
番地を形成した符号板、2は移動体と一体となつて移動
し、符号板1の符号を読み取る検出器、3、4はそれぞ
れ右側番地と左側番地を一定の相関で決定する右側番地
発生器および左側番地発生器で、例えば右または左への
移動に伴つて得られる絶対番地が単純増加あるいは単純
減少のBCD符号であるときは、″1’’を加算する加
算器および゛゛1”を減算する減算器である。5、6、
7はそれぞれ前記検出器2、右側、左側番地発生器3、
4の出力を記憶するレジスタで、同一番地、右側番地、
左側番地を記憶することになる。In this figure, 1 is a code plate that forms an absolute address installed along the moving path, 2 is a detector that moves together with the moving body and reads the code on code plate 1, and 3 and 4 are on the right side, respectively. For example, when the absolute address obtained by moving to the right or left is a BCD code of simple increase or decrease in the right-hand address generator and the left-hand address generator that determine the address and the left-hand address with a certain correlation, These are an adder that adds "1" and a subtracter that subtracts "1". 5, 6,
7 are the detector 2, right side address generator 3, and left side address generator 3, respectively.
A register that stores the output of 4, the same address, right address,
The address on the left side will be memorized.
8、9、1口は前記レジスタ5、6、7の各出力と検出
器2の出力とをそれぞれ比較する排他的論理和回路であ
り、両入力が一致したとき“1’’を出力し、不一致で
あれば”0”を出力する。8, 9, and 1 are exclusive OR circuits that compare the outputs of the registers 5, 6, and 7 with the output of the detector 2, and output "1" when both inputs match. If they do not match, "0" is output.
11は前記排他的論理和回路8,9,10の出力を入力
とする論理和回路、12は前記論理和回路11の出力を
入力とするフリツプフロツプ、13は2相のクロツクを
発生するクロツク発生器、14は論理積回路、15は前
番地に隣接した番地を発生して記憶する回路部分、16
は検出された符号と記憶された符号を比較する回路部分
である。11 is an OR circuit that receives the outputs of the exclusive OR circuits 8, 9, and 10; 12 is a flip-flop that receives the output of the OR circuit 11; and 13 is a clock generator that generates two-phase clocks. , 14 is an AND circuit, 15 is a circuit portion that generates and stores an address adjacent to the previous address, 16
is a circuit portion that compares the detected code and the stored code.
次に動作について説明する。検出器2によつて読み取ら
れた符号は排他的論理和回路8,9,10でレジスタ5
,6,7の出力と比較され、以前の番地で同一であれば
排他的論理和回路8の出力が゛1―以前の番地の右側の
番地に一致すれば排他的論理和回路9の出力が゛1−そ
して以前の番地の左側の番地に一致すれば排他的論理和
回路10の出力が゛1”になり、これらの出力は論理和
回路11を通つてフリツプフロツプ12の入力に接続さ
れる。フリツプフロツプ12はクロツク発生器13のク
ロツクで同期化されて動作し、論理和回路11の状態を
監視して出力する。したがつて検出器2の出力がレジス
タ5,6,7の出力のいずれかと一致すれば、フリツプ
フロツプ12の出力Qは11゛となり、不一致であれば
出力Qが”1゛になる。すなわち、出力Qが゛1゛のと
きは正しい符号、出力Qが゛1゜゛のときは誤つた符号
である。正しい符号のときは論理積回路14の出力が゛
1゛となつて回路部分15を動作させて、レジスタ5,
6,7の内容を書き直す。したがつてレジスタ5の出力
は常に正しい現在の番地を出力することになる。ただし
、以上の動作が正確に行われるためには、初期状態にお
いて符号板1と検出器2の位置、およびレジスタ5,6
,7の内容を一致させる必要があり、また、クロツク発
生器13の周期は移動速度にくらべ十分に短いことが条
件である。Next, the operation will be explained. The code read by the detector 2 is sent to the register 5 by exclusive OR circuits 8, 9, and 10.
, 6, and 7, and if they are the same at the previous address, the output of the exclusive OR circuit 8 is ``1''. ``1'' and if the address matches the address to the left of the previous address, the output of the exclusive OR circuit 10 becomes ``1'', and these outputs are connected to the input of the flip-flop 12 through the OR circuit 11. The flip-flop 12 operates in synchronization with the clock of the clock generator 13, and monitors the state of the OR circuit 11 and outputs it. If they match, the output Q of the flip-flop 12 becomes 11°, and if they do not match, the output Q becomes “1”. That is, when the output Q is "1", it is a correct code, and when the output Q is "1", it is an incorrect code. When the sign is correct, the output of the AND circuit 14 becomes "1", operating the circuit section 15, and registers 5,
Rewrite the contents of 6 and 7. Therefore, the output of register 5 will always output the correct current address. However, in order for the above operation to be performed accurately, the positions of the code plate 1 and the detector 2, and the registers 5 and 6 must be adjusted in the initial state.
, 7 must match, and the period of the clock generator 13 must be sufficiently short compared to the moving speed.
以上説明したように、この発明は現在の絶対番地に隣接
する絶対番地を発生させ予想番地として記憶しておき、
移動体が移動して新しい絶対番地になつたときこの絶対
番地と前記予想番地とを比較して不一致のときは誤りと
する方法であり、絶対番地としての一連の2進符号その
ものが冗長度の高いことを利用して位置検出の誤りを検
出するものであるため、特に冗長ビツトを付け加えなく
てや誤検出を行うことができる。したがつて従来の方法
にくらべて通路に沿つて設置する符号板に要する経済的
な負担を軽減することができる。また、従来の方法と併
用して位置検出の信頼度をさらに上げることができる等
の利点がある。As explained above, the present invention generates an absolute address adjacent to the current absolute address and stores it as a predicted address.
When a mobile object moves and a new absolute address is obtained, this absolute address is compared with the expected address and if they do not match, it is determined as an error.The series of binary codes as the absolute address itself has a redundancy Since the error in position detection is detected by utilizing the high value, erroneous detection can be performed without particularly adding redundant bits. Therefore, compared to the conventional method, the economic burden required for the code plates installed along the path can be reduced. Further, there are advantages such as the ability to further increase the reliability of position detection when used in combination with conventional methods.
図面はこの発明の一実施例の構成を示すプロツク図であ
る。
図中、1は符号板、2は検出器、3は右側番地発生器、
4は左側番地発生器、5,6,7はレジスタ、8,9,
10は排他的論理和回路、11は論理和回路、12はフ
リツプフロツプ、13はクロツク発生器、14は論理積
回路である。The drawing is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 1 is a code plate, 2 is a detector, 3 is a right-hand address generator,
4 is the left address generator, 5, 6, 7 are registers, 8, 9,
10 is an exclusive OR circuit, 11 is an OR circuit, 12 is a flip-flop, 13 is a clock generator, and 14 is an AND circuit.
Claims (1)
区切り、区切られた区間にはそれぞれ2進符号の絶対番
地を与え、移動体において前記2進符号を読み取ること
によつてその位置を検出する移動位置検出装置において
、現在の絶対番地に隣接する絶対番地を発生させ予想番
地として記憶しておき、移動体が移動し新しい絶対番地
になつたときこの絶対番地と前記予想番地とを比較して
不一致のときは誤りとすることを特徴とする移動体位置
検出装置における誤り検出方法。1. Divide the path that requires detection of the position of a moving object into certain sections, give each section an absolute address in binary code, and read the binary code at the moving object to determine its position. In the mobile position detection device that detects, an absolute address adjacent to the current absolute address is generated and stored as a predicted address, and when the moving object moves and becomes a new absolute address, this absolute address is compared with the predicted address. An error detection method in a mobile body position detecting device, characterized in that an error is determined when the values do not match.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3352176A JPS5926886B2 (en) | 1976-03-29 | 1976-03-29 | Error detection method in mobile body position detection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3352176A JPS5926886B2 (en) | 1976-03-29 | 1976-03-29 | Error detection method in mobile body position detection device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS52117153A JPS52117153A (en) | 1977-10-01 |
JPS5926886B2 true JPS5926886B2 (en) | 1984-07-02 |
Family
ID=12388838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3352176A Expired JPS5926886B2 (en) | 1976-03-29 | 1976-03-29 | Error detection method in mobile body position detection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5926886B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5990198A (en) * | 1982-11-12 | 1984-05-24 | 三菱電機株式会社 | Position measuring apparatus |
JPS59166126U (en) * | 1983-04-22 | 1984-11-07 | 株式会社安川電機 | Absolute type rotary encoder with error check slit |
JPS63150624A (en) * | 1986-12-16 | 1988-06-23 | Yoshida Kogyo Kk <Ykk> | Judging method for pulse of encoder |
JPH0668448B2 (en) * | 1987-12-28 | 1994-08-31 | 三菱化成株式会社 | Position measuring device |
-
1976
- 1976-03-29 JP JP3352176A patent/JPS5926886B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS52117153A (en) | 1977-10-01 |
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